4.2 Benchmarks

Since this functionality is implemented directly after boot, the Flash wait states and phase-locked loop (PLL) are not configured and, therefore, run at their default values. The Flash wait states are configured for 15 cycles and SYSCLKOUT of OSCCLK/2 for the F280xx/F281x devices and OSCCLK/4 for F2833x devices. Using the profiling feature of Code Composer Studio, the execution time can be measured. Table 3 shows the timing information for each F28xxx DSC by measuring the time elapsed from boot to the first instruction within the main( ) function for the examples provided in the associated code files. As shown, the execution time for each platform increases; this is due to an increase in code size and decreasing SYSCLKOUT.