SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
The PLL1 Configuration function configures the PLL1 registers. This function takes two arguments, as shown below.
The PLL1 configuration register is shown in Figure 30 and described in Table 18.
| 31 | 24 | 23 | 16 | 15 | 8 | 7 | 0 |
| Arg1 | PLLM | POSTDIV | PLLDIV1 | PLLDIV2 | ||||||||||||||||||||||||||||
| Arg2 | Reserved | PLLDIV3 | ||||||||||||||||||||||||||||||
| Bit | Field | Value | Description | |
|---|---|---|---|---|
| Arg1 | 31-24 | PLLM | Value to be programmed to the PLL Multiplier register. | |
| 23-18 | POSTDIV | Value to be programmed to PLL POSTDIV register, used to divide the output of the PLL multiplier. | ||
| 15-8 | PLLDIV1 | Values to be programmed to the PLLDIV1, PLLDIV2, and PLLDIV3 registers, used to generate SYSCLK1, SYSCLK2, and SYSCLK3. | ||
| 7-0 | PLLDIV2 | Values to be programmed to the PLLDIV1, PLLDIV2, and PLLDIV3 registers, used to generate SYSCLK1, SYSCLK2, and SYSCLK3. | ||
| Arg2 | 31-8 | Reserved | 0 | Reserved |
| 7-0 | PLLDIV3 | Values to be programmed to the PLLDIV1, PLLDIV2, and PLLDIV3 registers, used to generate SYSCLK1, SYSCLK2, and SYSCLK3. |