SPRABA5D January 2014 – January 2019 AM1802 , AM1802 , AM1806 , AM1806 , AM1808 , AM1808 , AM1810 , AM1810
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Using the AM18xx Bootloader
- Trademarks
- 1 Introduction
- 2 Boot Modes
- 3 Non-AIS Boot Modes
- 4
Application Image Script (AIS) Boot
- 4.1 Section Load Command (0x58535901)
- 4.2 Section Fill Command (0x5853590A)
- 4.3 Enable CRC Command (0x58535903)
- 4.4 Disable CRC Command (0x58535904)
- 4.5 Validate CRC Command (0x58535902)
- 4.6 Jump & Close Command (0x58535906)
- 4.7 Jump Command (0x58535905)
- 4.8 Sequential Read Enable Command (0x58535963)
- 4.9 Function Execute Command (0x5853590D)
- 4.10 Boot Table Command (0x58535907)
- 5
AISgen: Tool to Generate Boot Script (AIS Image)
- 5.1 Installation
- 5.2 Getting Started
- 5.3
Generating AIS
- 5.3.1 Boot Mode and Boot Peripheral Setup
- 5.3.2 Phase-Locked Loop (PLL) Setup
- 5.3.3 Synchronous Dynamic Random Access Memory (SDRAM) Setup
- 5.3.4 DDR Setup
- 5.3.5 PSC Setup
- 5.3.6 Pin Multiplexing Setup
- 5.3.7 Application File Selection
- 5.3.8 AIS File Selection
- 5.3.9 Status and Messages
- 5.3.10 Additional AIS Options
- 5.3.11 Command Line Usage
- 6 Master Boot – Booting From a Slave Memory Device
- 7 Slave Boot – Booting From an External Master Host
- 8 UART Boot Host - Using Your PC as a UART Boot Master
- 9 Boot Requirements, Constraints and Default Settings
- 10 References
- A Boot Mode Selection Table
- B Details of Supported NAND Devices
- C CRC Computation Algorithm
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D Details of Pre-Defined ROM Functions
- D.1 PLL0 Configuration (Index = 0, Argument Count = 2)
- D.2 PLL1 Configuration (Index = 1, Argument Count = 2)
- D.3 Clock Configuration (Index = 2, Argument Count = 1)
- D.4 mDDR/DDR2 Controller Configuration (Index = 3, Argument Count = 8)
- D.5 EMIFA SDRAM Configuration (Index = 4, Argument Count = 5)
- D.6 EMIFA Async Configuration (Index = 5, Argument Count = 5)
- D.7 PLL and Clock Configuration (Index = 6, Argument Count = 3)
- D.8 Power and Sleep Configuration (PSC) (Index = 7, Argument Count = 1)
- D.9 Pinmux Configuration (Index = 8, Argument Count = 3)
- E ROM Revision History
- Revision History
7.2 Start-Word Synchronization (SWS)
After power ON reset (POR), the bootloader takes some time to initialize and configure the boot peripheral. Similarly, the host also takes its own time to initialize and prepare to boot the device. A SWS mechanism is used to synchronize the device and host after POR.
To achieve SWS, the host repeatedly sends transmit-start-word (XMT_START) to the device until it receives the proper response (receive-start-word or RECV_START) from the device.
Figure 22. Flowchart: Start-Word Synchronization For the SPI and I2C slave modes, the bootloader operates the SPI/I2C peripheral in 16-bit mode, so that both start words are 16-bit (0x5853 & 0x5253). For the UART-boot mode, the bootloader operates the UART peripheral in 8-bit mode, so that both start words are 8-bit (0x58 & 0x52).
NOTE
While start-words are 8-/16-bit, all other data including op-codes and CRC are 32-bit, and all 32 bits need to be transmitted to the bootloader regardless of the boot mode.
For UART boot mode, the bootloader transmits the ASCII string BOOTME to the host before it is ready to begin SWS. This transmission occurs only once immediately following reset, and the host should not initiate SWS until after receiving this string. SWS and all subsequent steps proceed as normal using binary data transmission; no other data should be sent or received in ASCII format.
NOTE
When the bootloader begins running, the device’s PLL is configured in bypass mode. If the external host device is fast enough, it will need to insert a delay after each transmission to allow the bootloader time to finish processing the previous data. The need for such delays can be alleviated later in the boot process by configuring the PLL via the Function Execute Command.