The write-leveling process in the DDR3 interface imposes a limit on the maximum and minimum skew between the command delay and the data delay. If these limits are exceeded, the DDR3 interface may fail the write leveling process and data corruption may occur. These limits are sufficiently large that well-controlled topologies will not likely exceed the limits.

The command delay is defined as delay for the clock, command, control, and address group signals from the DSP to a given SDRAM. The data delay is the delay for the data group signals to that same SDRAM. The write-leveling result is effectively the difference, or skew, between these two delays.

The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM. The write-leveling logic has an upper limit which is the lower of 1.75 clock periods or 2500 ps. For instance, when operating at 1600MT/s, the clock is 800MHz which has a period of 1250ps. The maximum skew is 1.75 clock periods or 2187ps. At a propagation delay of 180ps per inch, this limits the write-leveling routing skew length to just over 12.1 inches.

The minimum write leveling skew occurs when the command delay is less than the data delay. The minimum write-leveling skew is -0.75 times the clock period. At 1600MT/s, this minimum skew is 937ps or about 5.2 inches. The DDR3 PHY implemented on KeyStone II can operate within these limits without the need to invert the clock to the DDR3 SDRAMs.