SPRABI1D January   2018  – July 2022 66AK2E05 , 66AK2G12 , 66AK2H06 , 66AK2H12 , 66AK2H14 , 66AK2L06 , AM5K2E02 , AM5K2E04 , SM320C6678-HIREL , TMS320C6652 , TMS320C6654 , TMS320C6655 , TMS320C6657 , TMS320C6670 , TMS320C6671 , TMS320C6672 , TMS320C6674 , TMS320C6678

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Background
  4. 3 Migrating Designs From DDR2 to DDR3 (Features and Comparisons)
    1. 3.1 Topologies
      1. 3.1.1 Balanced Line Topology
        1. 3.1.1.1 Balanced Line Topology Issues
      2. 3.1.2 Fly-By Topology
        1. 3.1.2.1 Balanced Line Topology Issues
    2. 3.2 ECC (Error Correction)
    3. 3.3 DDR3 Features and Improvements
      1. 3.3.1 Read Leveling
      2. 3.3.2 Write Leveling
      3. 3.3.3 Pre-fetch
      4. 3.3.4 ZQ Calibration
      5. 3.3.5 Reset Pin Functionality
      6. 3.3.6 Additional DDR2 to DDR3 Differences
  5. 4 Prerequisites
    1. 4.1 High Speed Designs
    2. 4.2 JEDEC DDR3 Specification – Compatibility and Familiarity
    3. 4.3 Memory Types
    4. 4.4 Memory Speeds
    5. 4.5 Addressable Memory Space
    6. 4.6 DDR3 SDRAM/UDIMM Memories, Topologies, and Configurations
      1. 4.6.1 Topologies
      2. 4.6.2 Configurations
        1. 4.6.2.1 Memories – SDRAM Selection Criteria
    7. 4.7 DRAM Electrical Interface Requirements
      1. 4.7.1 Slew
      2. 4.7.2 Overshoot and Undershoot Specifications
        1. 4.7.2.1 Overshoot and Undershoot Example Calculations
      3. 4.7.3 Typical DDR3 AC and DC Characteristics
      4. 4.7.4 DDR3 Tolerances and Noise – Reference Signals
  6. 5 Package Selection
    1. 5.1 Summary
      1. 5.1.1 ×4 SDRAM
      2. 5.1.2 ×8 SDRAM
      3. 5.1.3 ×16 SDRAM
      4. 5.1.4 ×32 SDRAM
      5. 5.1.5 ×64 SDRAM
  7. 6 Physical Design and Implementation
    1. 6.1 Electrical Connections
      1. 6.1.1 Pin Connectivity and Unused Pins – SDRAM Examples
      2. 6.1.2 Pin Connectivity – ECC UDIMM and Non-ECC UDIMM Examples
    2. 6.2 Signal Terminations
      1. 6.2.1 External Terminations – When Using Read and Write Leveling
      2. 6.2.2 External Terminations – When Read and Write Leveling is Not Used
      3. 6.2.3 Internal Termination – On-Die Terminations
      4. 6.2.4 Active Terminations
      5. 6.2.5 Passive Terminations
      6. 6.2.6 Termination Component Selection
    3. 6.3 Mechanical Layout and Routing Considerations
      1. 6.3.1 Routing Considerations – SDRAMs
        1. 6.3.1.1  Mechanical Layout – SDRAMs
        2. 6.3.1.2  Stack Up – SDRAMs
        3. 6.3.1.3  Routing Rules – General Overview (SDRAMs)
        4. 6.3.1.4  Routing Rules – Address and Command Lines (SDRAMs)
        5. 6.3.1.5  Routing Rules – Control Lines (SDRAMs)
        6. 6.3.1.6  Routing Rules – Data Lines (SDRAMs)
        7. 6.3.1.7  Routing Rules – Clock Lines (SDRAMs)
        8. 6.3.1.8  Routing Rules – Power (SDRAMs)
        9. 6.3.1.9  Write Leveling Limit Impact on Routing – KeyStone I
        10. 6.3.1.10 Round-Trip Delay Impact on Routing – KeyStone I
        11. 6.3.1.11 Write Leveling Limit Impact on Routing – KeyStone II
        12. 6.3.1.12 Round-Trip Delay Impact on Routing – KeyStone II
      2. 6.3.2 Routing Considerations – UDIMMs
        1. 6.3.2.1 Mechanical Layout – UDIMMs
        2. 6.3.2.2 Stack Up – UDIMMs
        3. 6.3.2.3 Routing Rules – General Overview (UDIMMs)
        4. 6.3.2.4 Routing Rules – Address and Command Lines (UDIMMs)
        5. 6.3.2.5 Routing Rules – Control Lines (UDIMMs)
        6. 6.3.2.6 Routing Rules – Data Lines (UDIMMs)
        7. 6.3.2.7 Routing Rules – Clock Lines (UDIMMs)
        8. 6.3.2.8 Routing Rules – Power (UDIMMs)
        9. 6.3.2.9 Write-Leveling Limit Impact on Routing
    4. 6.4 Timing Considerations
    5. 6.5 Impedance Considerations
      1. 6.5.1 Routing Impedances – KeyStone I Devices
        1. 6.5.1.1 Data Group Signals
        2. 6.5.1.2 Fly-By Signals
      2. 6.5.2 Routing Impedances – KeyStone II Devices
        1. 6.5.2.1 Data Group Signals
        2. 6.5.2.2 Fly-By Signals
      3. 6.5.3 Comparison to JEDEC UDIMM Impedance Recommendations
    6. 6.6 Switching and Output Considerations
  8. 7 Simulation and Modeling
    1. 7.1 Simulation and Modeling
    2. 7.2 Tools
    3. 7.3 Models
    4. 7.4 TI Commitment
  9. 8 Power
    1. 8.1 DDR3 SDRAM Power Requirements
      1. 8.1.1 Vref Voltage Requirements
      2. 8.1.2 VTT Voltage Requirements
    2. 8.2 DSP DDR3 Power Requirements
    3. 8.3 DDR3 Power Estimation
    4. 8.4 DSP DDR3 Interface Power Estimation
    5. 8.5 Sequencing – DDR3 and DSP
  10. 9 Disclaimers
  11. 10References
  12. 11Revision History

6.1 Electrical Connections

This section discusses the proper electrical interface between JEDEC-compliant DDR3 SDRAMs and UDIMMs to the Texas Instruments KeyStone DSP family DDR3 controller. These sections also provide details for the electrical pin connectivity between the DSP DDR3 interface and DDR3 SDRAM or UDIMM. This is not an all-inclusive listing of available parts as DRAM manufacturers are continuously developing higher density parts or obsoleting others. It should also be noted that not all DSPs will have the same bus width. For details, see the device-specific data sheet. This section assumes both 32-bit and 64-bit wide buses are used.
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