The write-leveling process in the DDR3 interface imposes a limit on the maximum and minimum skew between the command delay and the data delay. If these limits are exceeded, the DDR3 interface may fail the write leveling process and data corruption may occur. These limits are sufficiently large that well-controlled topologies will not likely exceed the limits.

The command delay is defined as delay for the clock, command, control, and address group signals from the DSP to a given SDRAM. The data delay is the delay for the data group signals to that same SDRAM. The write-leveling result is effectively the difference, or skew, between these two delays.

The maximum write-leveling skew is the largest difference between the two delays in the topology to a single SDRAM. Likewise, the minimum write-leveling skew is the smallest difference between the two delays in the topology to a single SDRAM.

The write-leveling logic has a theoretical upper limit of 2500 ps. This limit does not scale with SDRAM data rate. The theoretical upper limit equates to two full clock cycles when the clock frequency is 800 MHz for DDR3-1600. It is reduced by half a clock cycle when invert clock out is enabled, as this effectively lengthens the clock by this amount.

The following set of equations provides an approximation of the maximum and minimum write-leveling skew allowed:

• ddrclkout_period – period of reference clock the DSP is providing to SDRAM
• tWLS – from JEDEC DDR3 SDRAM specification, write-leveling setup time from rising CK, CK crossing to rising DQS, DQS crossing
• tJIT(per, lck) – clock period jitter during DLL locking period
• command_delay – delay for the clock, command, control and address group signals from the DSP to a given SDRAM
• data_delay – delay for the data group signals to that same SDRAM
• write_leveling_skew – defined as the value command_delay - data_delay
• margin - additional margin added for preliminary use

Maximum write-leveling skew:

• Case 1: Invert clock disabled
  • write_leveling_skew < 2500 ps - tWLS - tJIT(per, lck) - margin
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • command_delay + (0.5 *ddrclkout_period) - data_delay = write_leveling_skew< 2500 ps - tWLS - tJIT(per, lck) - margin
  • write_leveling_skew < 2500 ps - tWLS - tJIT(per, lck) - (0.5 *ddrclkout_period) - margin

Minimum write-leveling skew:

• Case 1: Invert clock disabled
  • write_leveling_skew > tWLS + tJIT(per, lck) + margin
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • command_delay + (0.5 *ddrclkout_period) - data_delay = write_leveling_skew > tWLS + tJIT(per, lck) + margin
  • write_leveling_skew > tWLS + tJIT(per, lck) - (0.5 *ddrclkout_period) + margin

tWLS and tJIT(per, lck) are standard JEDEC DDR3 SDRAM timing parameters that can be obtained from the specific data sheet of the SDRAM chosen.

Based on the previous equations, the following calculations and summary table shows the write-leveling skew limitations for both invert clock out enabled and disabled given the DDR3-1333 and DDR3-1600 JEDEC SDRAM specification. The first column for each speed-grade category lists the maximum write-leveling skew in picoseconds. The second column for each lists the maximum write-leveling skew in inches, assuming a signal propagation rate of 180 ps/in.

For DDR3-1333:

• ddrclkout_period = 1500 ps
• tWLS = 195 ps
• tJIT(per, lck) = ±70 ps
• margin = 100 ps

Maximum write-leveling skew:

• Case 1: Invert clock disabled
  • write_leveling_skew < 2500 ps - tWLS - tJIT(per, lck) - margin
  • write_leveling_skew < 2500 ps - 195 ps - 70 ps -100 ps
  • write_leveling_skew < 2500 ps - 195 ps - 70 ps -100 ps
  • write_leveling_skew < 2135 ps
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • write_leveling_skew < 2500 ps - tWLS - tJIT(per, lck) - (0.5 *ddrclkout_period) - margin
  • write_leveling_skew < 2500 ps - 195 ps - 70 ps - (0.5 *1500 ps) - 100 ps
  • write_leveling_skew < 1385 ps

Minimum write-leveling skew:

• Case 1: Invert Clock disabled
  • write_leveling_skew > tWLS + tJIT(per, lck) + margin
  • write_leveling_skew > 195 ps + 70 ps + 100 ps
  • write_leveling_skew > 365 ps
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • write_leveling_skew > tWLS + tJIT(per, lck) - (0.5 *ddrclkout_period) + margin
  • write_leveling_skew > 195 ps + 70 ps - (0.5 *1500 ps) + 100 ps
  • write_leveling_skew > -385 ps

For DDR3-1600:

• ddrclkout_period = 1250 ps
• tWLS = 165 ps
• tJIT(per, lck) = ± 60 ps
• margin = 100 ps

Maximum write-leveling skew:

• Case 1: Invert clock disabled
  • write_leveling_skew < 2500 ps - 165 ps - 60 ps -100 ps
  • write_leveling_skew < 2500 ps - 165 ps - 60 ps -100 ps
  • write_leveling_skew < 2175 ps
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • write_leveling_skew < 2500 ps - 165 ps - 60 ps - (0.5 *1250 ps) - 100 ps
  • write_leveling_skew < 1610 ps

Minimum write-leveling skew:

• Case 1: Invert clock disabled
  • write_leveling_skew > 165 ps + 60 ps + 100 ps
  • write_leveling_skew > 325 ps
• Case 2: Invert clock enabled (adds an additional half-clock period of delay to the command delay term)
  • write_leveling_skew > 165 ps + 60 ps - (0.5 *1250 ps) + 100 ps
  • write_leveling_skew > -300 ps