SPRAC21A June   2016  – June 2019 OMAP-L132 , OMAP-L138 , TDA2E , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX , TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

 

  1.   TDA2xx and TDA2ex Performance
    1.     Trademarks
    2. 1  SoC Overview
      1. 1.1 Introduction
      2. 1.2 Acronyms and Definitions
      3. 1.3 TDA2xx and TDA2ex System Interconnect
      4. 1.4 Traffic Regulation Within the Interconnect
        1. 1.4.1 Bandwidth Regulators
        2. 1.4.2 Bandwidth Limiters
        3. 1.4.3 Initiator Priority
      5. 1.5 TDA2xx and TDA2ex Memory Subsystem
        1. 1.5.1 Controller/PHY Timing Parameters
        2. 1.5.2 Class of Service
        3. 1.5.3 Prioritization Between DMM/SYS PORT or MPU Port to EMIF
      6. 1.6 TDA2xx and TDA2ex Measurement Operating Frequencies
      7. 1.7 System Instrumentation and Measurement Methodology
        1. 1.7.1 GP Timers
        2. 1.7.2 L3 Statistic Collectors
    3. 2  Cortex-A15
      1. 2.1 Level1 and Level2 Cache
      2. 2.2 MMU
      3. 2.3 Performance Control Mechanisms
        1. 2.3.1 Cortex-A15 Knobs
        2. 2.3.2 MMU Page Table Knobs
      4. 2.4 Cortex-A15 CPU Read and Write Performance
        1. 2.4.1 Cortex-A15 Functions
        2. 2.4.2 Setup Limitations
        3. 2.4.3 System Performance
          1. 2.4.3.1 Cortex-A15 Stand-Alone Memory Read, Write, Copy
          2. 2.4.3.2 Results
    4. 3  System Enhanced Direct Memory Access (System EDMA)
      1. 3.1 System EDMA Performance
        1. 3.1.1 System EDMA Read and Write
        2. 3.1.2 System EDMA Results
      2. 3.2 System EDMA Observations
    5. 4  DSP Subsystem EDMA
      1. 4.1 DSP Subsystem EDMA Performance
        1. 4.1.1 DSP Subsystem EDMA Read and Write
        2. 4.1.2 DSP Subsystem EDMA Results
      2. 4.2 DSP Subsystem EDMA Observations
    6. 5  Embedded Vision Engine (EVE) Subsystem EDMA
      1. 5.1 EVE EDMA Performance
        1. 5.1.1 EVE EDMA Read and Write
        2. 5.1.2 EVE EDMA Results
      2. 5.2 EVE EDMA Observations
    7. 6  DSP CPU
      1. 6.1 DSP CPU Performance
        1. 6.1.1 DSP CPU Read and Write
        2. 6.1.2 Code Setup
          1. 6.1.2.1 Pipeline Copy
          2. 6.1.2.2 Pipeline Read
          3. 6.1.2.3 Pipeline Write
          4. 6.1.2.4 L2 Stride-Jmp Copy
          5. 6.1.2.5 L2 Stride-Jmp Read
          6. 6.1.2.6 L2 Stride-Jmp Write
      2. 6.2 DSP CPU Observations
      3. 6.3 Summary
    8. 7  Cortex-M4 (IPU)
      1. 7.1 Cortex-M4 CPU Performance
        1. 7.1.1 Cortex-M4 CPU Read and Write
        2. 7.1.2 Code Setup
        3. 7.1.3 Cortex-M4 Functions
        4. 7.1.4 Setup Limitations
      2. 7.2 Cortex-M4 CPU Observations
        1. 7.2.1 Cache Disable
        2. 7.2.2 Cache Enable
      3. 7.3 Summary
    9. 8  USB IP
      1. 8.1 Overview
      2. 8.2 USB IP Performance
        1. 8.2.1 Test Setup
        2. 8.2.2 Results and Observations
        3. 8.2.3 Summary
    10. 9  PCIe IP
      1. 9.1 Overview
      2. 9.2 PCIe IP Performance
        1. 9.2.1 Test Setup
        2. 9.2.2 Results and Observations
    11. 10 IVA-HD IP
      1. 10.1 Overview
      2. 10.2 H.264 Decoder
        1. 10.2.1 Description
        2. 10.2.2 Test Setup
        3. 10.2.3 Test Results
      3. 10.3 MJPEG Decoder
        1. 10.3.1 Description
        2. 10.3.2 Test Setup
        3. 10.3.3 Test Results
    12. 11 MMC IP
      1. 11.1 MMC Read and Write Performance
        1. 11.1.1 Test Description
        2. 11.1.2 Test Results
      2. 11.2 Summary
    13. 12 SATA IP
      1. 12.1 SATA Read and Write Performance
        1. 12.1.1 Test Setup
        2. 12.1.2 Observations
          1. 12.1.2.1 RAW Performance
          2. 12.1.2.2 SDK Performance
      2. 12.2 Summary
    14. 13 GMAC IP
      1. 13.1 GMAC Receive/Transmit Performance
        1. 13.1.1 Test Setup
        2. 13.1.2 Test Description
          1. 13.1.2.1 CPPI Buffer Descriptors
        3. 13.1.3 Test Results
          1. 13.1.3.1 Receive/Transmit Mode (see )
          2. 13.1.3.2 Receive Only Mode (see )
          3. 13.1.3.3 Transmit Only Mode (see )
      2. 13.2 Summary
    15. 14 GPMC IP
      1. 14.1 GPMC Read and Write Performance
        1. 14.1.1 Test Setup
          1. 14.1.1.1 NAND Flash
          2. 14.1.1.2 NOR Flash
        2. 14.1.2 Test Description
          1. 14.1.2.1 Asynchronous NAND Flash Read/Write Using CPU Prefetch Mode
          2. 14.1.2.2 Asynchronous NOR Flash Single Read
          3. 14.1.2.3 Asynchronous NOR Flash Page Read
          4. 14.1.2.4 Asynchronous NOR Flash Single Write
        3. 14.1.3 Test Results
      2. 14.2 Summary
    16. 15 QSPI IP
      1. 15.1 QSPI Read and Write Performance
        1. 15.1.1 Test Setup
        2. 15.1.2 Test Results
        3. 15.1.3 Analysis
          1. 15.1.3.1 Theoretical Calculations
          2. 15.1.3.2 % Efficiency
      2. 15.2 QSPI XIP Code Execution Performance
      3. 15.3 Summary
    17. 16 Standard Benchmarks
      1. 16.1 Dhrystone
        1. 16.1.1 Cortex-A15 Tests and Results
        2. 16.1.2 Cortex-M4 Tests and Results
      2. 16.2 LMbench
        1. 16.2.1 LMbench Bandwidth
          1. 16.2.1.1 TDA2xx and TDA2ex Cortex-A15 LMbench Bandwidth Results
          2. 16.2.1.2 TDA2xx and TDA2ex Cortex-M4 LMBench Bandwidth Results
          3. 16.2.1.3 Analysis
        2. 16.2.2 LMbench Latency
          1. 16.2.2.1 TDA2xx and TDA2ex Cortex-A15 LMbench Latency Results
          2. 16.2.2.2 TDA2xx and TDA2ex Cortex-M4 LMbench Latency Results
          3. 16.2.2.3 Analysis
      3. 16.3 STREAM
        1. 16.3.1 TDA2xx and TDA2ex Cortex-A15 STREAM Benchmark Results
        2. 16.3.2 TDA2xx and TDA2ex Cortex-M4 STREAM Benchmark Results
    18. 17 Error Checking and Correction (ECC)
      1. 17.1 OCMC ECC Programming
      2. 17.2 EMIF ECC Programming
      3. 17.3 EMIF ECC Programming to Starterware Code Mapping
      4. 17.4 Careabouts of Using EMIF ECC
        1. 17.4.1 Restrictions Due to Non-Availability of Read Modify Write ECC Support in EMIF
          1. 17.4.1.1 Un-Cached CPU Access of EMIF
          2. 17.4.1.2 Cached CPU Access of EMIF
          3. 17.4.1.3 Non CPU Access of EMIF Memory
          4. 17.4.1.4 Debugger Access of EMIF via the Memory Browser/Watch Window
          5. 17.4.1.5 Software Breakpoints While Debugging
        2. 17.4.2 Compiler Optimization
        3. 17.4.3 Restrictions Due to i882 Errata
        4. 17.4.4 How to Find Who Caused the Unaligned Quanta Writes After the Interrupt
      5. 17.5 Impact of ECC on Performance
    19. 18 DDR3 Interleaved vs Non-Interleaved
      1. 18.1 Interleaved versus Non-Interleaved Setup
      2. 18.2 Impact of Interleaved vs Non-Interleaved DDR3 for a Single Initiator
      3. 18.3 Impact of Interleaved vs Non-Interleaved DDR3 for Multiple Initiators
    20. 19 DDR3 vs DDR2 Performance
      1. 19.1 Impact of DDR2 vs DDR3 for a Single Initiator
      2. 19.2 Impact of DDR2 vs DDR3 for Multiple Initiators
    21. 20 Boot Time Profile
      1. 20.1 ROM Boot Time Profile
      2. 20.2 System Boot Time Profile
    22. 21 L3 Statistics Collector Programming Model
    23. 22 Reference
  2.   Revision History

3.1.2 System EDMA Results

NOTE

When using multiple TCs transferring data to DDR it is important to understand the impact of DDR page open and close on the overall DDR efficiency.

Table 9. System EDMA 1 TC Bandwidth for Different Source Destination Combinations With
GP Timer (Single TC)

No. Source Destination ACNT BCNT Size
(KB)		 Ideal Throughput (MB/s) Measured Bandwidth (MB/s) TC Utilization (%)
1 EMIF 0 DDR EMIF 0 DDR 65535 128 8192 4256 3274.08 76.93
2 OCMC RAM0 EMIF 0 DDR 65535 4 256 4256 3186.1 74.86
3 EMIF 0 DDR OCMC RAM0 65535 4 256 4256 3071.96 72.18
4 OCMC RAM2 OCMC RAM2 65535 8 512 4256 3942 92.6
5 DSP L2 EMIF 0 DDR 65535 4 256 4256 3015.59 70.86
6 EMIF 0 DDR DSP L2 65535 4 256 4256 2956.82 69.47
7 IVA SL2 EMIF 0 DDR 65535 4 256 4256 1486.21 34.92
8 EMIF 0 DDR IVA SL2 65535 4 256 4256 1486.77 34.93
9 IVA SL2 DSP L2 65535 4 256 4256 1486.21 34.92
10 DSP L2 IVA SL2 65535 4 256 4256 1486.21 34.92
11 DSP L2 OCMC RAM 65535 4 256 4256 3017.9 70.91
12 OCMC RAM DSP L2 65535 4 256 4256 3020.22 70.96
13 PRUSS1 IRAM EMIF 0 DDR 1024 12 12 800 287.55 35.94
14 EMIF 0 DDR PRUSS1 IRAM 1024 12 12 800 287.55 35.94
15 PRUSS1 DRAM0 EMIF 0 DDR 1024 8 8 800 287.33 35.92
16 EMIF 0 DDR PRUSS1 DRAM0 1024 8 8 800 285.99 35.75
17 PRUSS1 DRAM1 EMIF 0 DDR 1024 8 8 800 286.66 35.83
18 EMIF 0 DDR PRUSS1 DRAM1 1024 8 8 800 285.99 35.75
19 PRUSS2 IRAM EMIF 0 DDR 1024 8 8 800 283.58 35.45
20 EMIF 0 DDR PRUSS2 IRAM 1024 8 8 800 281.86 35.23
21 PRUSS2 DRAM0 EMIF 0 DDR 1024 12 12 800 275.76 34.47
22 EMIF 0 DDR PRUSS2 DRAM0 1024 12 12 800 272.73 34.09
23 PRUSS2 DRAM1 EMIF 0 DDR 1024 8 8 800 313.64 39.21
24 EMIF 0 DDR PRUSS2 DRAM1 1024 8 8 800 314.04 39.26
25 PRUSS2 DRAM2 EMIF 0 DDR 1024 32 32 800 313.84 39.23
26 EMIF 0 DDR PRUSS2 DRAM2 1024 32 32 800 313.84 39.23

Table 10. System EDMA 1 TC Bandwidth for Different Source Destination Combinations With
L3 Statistic Collectors (Single TC)

No. Source Destination ACNT BCNT Size
(KB)		 Ideal Throughput (MB/s) Measured Bandwidth (MB/s) TC Utilization (%)
1 EMIF 0 DDR EMIF 0 DDR 65535 128 8192 4256 3456 81
2 OCMC RAM0 EMIF 0 DDR 65535 4 256 4256 3300 78
3 EMIF 0 DDR OCMC RAM0 65535 4 256 4256 3400 80
4 OCMC RAM2 OCMC RAM2 65535 8 512 4256 3900 92
5 DSP L2 EMIF 0 DDR 65535 4 256 4256 3070 72
6 EMIF 0 DDR DSP L2 65535 4 256 4256 3070 72
7 IVA SL2 EMIF 0 DDR 65535 4 256 4256 1530 36
8 EMIF 0 DDR IVA SL2 65535 4 256 4256 1530 36
9 IVA SL2 DSP L2 65535 4 256 4256 1530 36
10 DSP L2 IVA SL2 65535 4 256 4256 1530 36
11 DSP L2 OCMC RAM 65535 4 256 4256 3070 72
12 OCMC RAM DSP L2 65535 4 256 4256 3070 72
13 PRUSS1 IRAM EMIF 0 DDR 1024 12 12 800 380 48
14 EMIF 0 DDR PRUSS1 IRAM 1024 12 12 800 380 48
15 PRUSS1 DRAM0 EMIF 0 DDR 1024 8 8 800 380 48
16 EMIF 0 DDR PRUSS1 DRAM0 1024 8 8 800 380 48
17 PRUSS1 DRAM1 EMIF 0 DDR 1024 8 8 800 380 48
18 EMIF 0 DDR PRUSS1 DRAM1 1024 8 8 800 380 48
19 PRUSS2 IRAM EMIF 0 DDR 1024 8 8 800 380 48
20 EMIF 0 DDR PRUSS2 IRAM 1024 8 8 800 380 48
21 PRUSS2 DRAM0 EMIF 0 DDR 1024 12 12 800 380 48
22 EMIF 0 DDR PRUSS2 DRAM0 1024 12 12 800 380 48
23 PRUSS2 DRAM1 EMIF 0 DDR 1024 8 8 800 380 48
24 EMIF 0 DDR PRUSS2 DRAM1 1024 8 8 800 380 48
25 PRUSS2 DRAM2 EMIF 0 DDR 1024 32 32 800 380 48
26 EMIF 0 DDR PRUSS2 DRAM2 1024 32 32 800 380 48

Table 11. System EDMA 2 TC Bandwidth for Multiple Source Destination Combinations With
GP Timer

No. Source Destination ACNT BCNT Size
(KB)		 Ideal Throughput (MB/s) Measured Bandwidth (MB/s) TC Utilization (%)
1 EMIF 0 DDR EMIF 0 DDR 65535 128 8192 4256 2594.2 60.95
2 OCMC RAM EMIF 0 DDR 65535 4 256 4256 2502.79 58.81
3 EMIF 0 DDR OCMC RAM 65535 4 256
4 DSP L2 EMIF 0 DDR 65535 4 256 4256 2501.2 58.77
5 EMIF 0 DDR DSP L2 65535 4 256
6 IVA SL2 EMIF 0 DDR 65535 4 256 4256 1516.78 35.64
7 EMIF 0 DDR IVA SL2 65535 4 256
8 IVA SL2 DSP L2 65535 4 256 4256 1515.03 3.56
9 DSP L2 IVA SL2 65535 4 256
10 DSP L2 OCMC RAM 65535 4 256 4256 3132.96 73.61
11 OCMC RAM DSP L2 65535 4 256
12 PRUSS1 IRAM EMIF 0 DDR 1024 12 12 800 311.53 38.94
13 EMIF 0 DDR PRUSS1 IRAM 1024 12 12
14 PRUSS1 DRAM0 EMIF 0 DDR 1024 8 8 800 321.84 40.23
15 EMIF 0 DDR PRUSS1 DRAM0 1024 8 8
16 PRUSS1 DRAM1 EMIF 0 DDR 1024 8 8 800 321.42 40.18
17 EMIF 0 DDR PRUSS1 DRAM1 1024 8 8
18 PRUSS2 IRAM EMIF 0 DDR 1024 8 8 800 305.61 38.2
19 EMIF 0 DDR PRUSS2 IRAM 1024 8 8
20 PRUSS2 DRAM0 EMIF 0 DDR 1024 12 12 800 307.77 38.47
21 EMIF 0 DDR PRUSS2 DRAM0 1024 12 12
22 PRUSS2 DRAM1 EMIF 0 DDR 1024 8 8 800 323.31 40.41
23 EMIF 0 DDR PRUSS2 DRAM1 1024 8 8
24 PRUSS2 DRAM2 EMIF 0 DDR 1024 32 32 800 323.21 40.4
25 EMIF 0 DDR PRUSS2 DRAM2 1024 32 32

Table 12. System EDMA 2 TC Bandwidth for Multiple Source Destination Combinations With
L3 Statistic Collectors

No. Source Destination ACNT BCNT Size
(KB)		 Ideal Throughput (MB/s) Measured Bandwidth (MB/s) TC Utilization (%)
1 EMIF 0 DDR EMIF 0 DDR 65535 128 8192 4256 3050 71.66
2 OCMC RAM EMIF 0 DDR 65535 4 256 4256 3143 73.85
3 EMIF 0 DDR OCMC RAM 65535 4 256
4 DSP L2 EMIF 0 DDR 65535 4 256 4256 3250 76.36
5 EMIF 0 DDR DSP L2 65535 4 256
6 IVA SL2 EMIF 0 DDR 65535 4 256 4256 1560 36.65
7 EMIF 0 DDR IVA SL2 65535 4 256
8 IVA SL2 DSP L2 65535 4 256 4256 1560 36.65
9 DSP L2 IVA SL2 65535 4 256
10 DSP L2 OCMC RAM 65535 4 256 4256 3250 76.36
11 OCMC RAM DSP L2 65535 4 256
12 PRUSS1 IRAM EMIF 0 DDR 1024 12 12 800 330 41.25
13 EMIF 0 DDR PRUSS1 IRAM 1024 12 12
14 PRUSS1 DRAM0 EMIF 0 DDR 1024 8 8 800 330 41.25
15 EMIF 0 DDR PRUSS1 DRAM0 1024 8 8
16 PRUSS1 DRAM1 EMIF 0 DDR 1024 8 8 800 330 41.25
17 EMIF 0 DDR PRUSS1 DRAM1 1024 8 8
18 PRUSS2 IRAM EMIF 0 DDR 1024 8 8 800 330 41.25
19 EMIF 0 DDR PRUSS2 IRAM 1024 8 8
20 PRUSS2 DRAM0 EMIF 0 DDR 1024 12 12 800 330 41.25
21 EMIF 0 DDR PRUSS2 DRAM0 1024 12 12
22 PRUSS2 DRAM1 EMIF 0 DDR 1024 8 8 800 330 41.25
23 EMIF 0 DDR PRUSS2 DRAM1 1024 8 8
24 PRUSS2 DRAM2 EMIF 0 DDR 1024 32 32 800 330 41.25
25 EMIF 0 DDR PRUSS2 DRAM2 1024 32 32
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