1 Introduction

Calculation of the bit timing parameters requires at least three inputs:

• The desired bit rate, which is common across the entire bus.
• An estimate of the propagation delay between the most distant nodes on the bus
• The CAN module clock frequency, which is used to derive the bitstream sampling clock

The propagation delay comes from two main sources: the speed of electromagnetic propagation along the bus wiring and extra delay due to transceivers, isolation, or other interface circuitry.

A bit timing calculator must provide at least five outputs:

• The baud rate prescaler (BRP), which determines the sampling clock period. A single period is referred to as a time quantum (Tq).
• The propagation delay expressed as a number of time quanta.
• The length of phase segment 1 (PhSeg1) in time quanta. In addition to determining the bit rate, phase segment 1 acts as a buffer that can be lengthened to resynchronize with the bitstream.
• The length of phase sergment 2 (PhSeg2) in time quanta. Phase segment 2 is like phase segment 1, but it occurs after the sampling point instead of before. Phase segment 2 can be shortened to resynchronize with the bit stream.
• The synchronization jump width (SJW) in time quanta. This is the maximum time by which the bit sampling period may be lengthened or shortened during each cycle to adjust for oscillator mismatch between nodes.

The calculator described in this document also outputs the number of time quanta per bit, the oscillator tolerance, the sampling point, and timing register values for the eCAN and D_CAN modules used on the TMS320C2000™ series of microcontrollers.