SPRACD8 June 2019 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726 , DRA745 , DRA746 , DRA74P , DRA750 , DRA756 , DRA75P , DRA76P , DRA77P , DRA780 , DRA781 , DRA782 , DRA783 , DRA786 , DRA787 , DRA790 , DRA791 , DRA793 , DRA797 , TDA2EG-17 , TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2P-ABZ , TDA2P-ACD , TDA2SA , TDA2SG , TDA2SX
Once the devices are defined in the device tree, it is important to configure the pinmux for the pads used for the video port. To ensure timings on DRA7xx SoCs, it is recommended to perform IODELAY configuration while in isolation in the first stage bootloader. Due to this, all the pinmux and IODELAY configuration is handled in the u-boot. Kernel does not handle any pinmux or IODELAY settings for video ports.
The following patch is an example of adding pinmux data to be configured in the u-boot. This adds entries for using VIN1A pads in the muxmode 6, which connects the signals to the vin3a video port and adds manual mode timing seed values for falling edge pclk.
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index c2b557f..fcd07fd 100644
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -538,6 +538,54 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
{MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */
{MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */
+#ifdef CONFIG_TARGET_DRA7XX_EVM_VISION
+ { VIN1B_CLK1, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1b_clk1.vin3a_clk0 */
+ { VIN1A_D16, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d16.vin3a_d0 */
+ { VIN1A_D17, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d17.vin3a_d1 */
+ { VIN1A_D18, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d18.vin3a_d2 */
+ { VIN1A_D19, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d19.vin3a_d3 */
+ { VIN1A_D20, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d20.vin3a_d4 */
+ { VIN1A_D21, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d21.vin3a_d5 */
+ { VIN1A_D22, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d22.vin3a_d6 */
+ { VIN1A_D23, (M6 | PIN_INPUT | MANUAL_MODE) }, /* vin1a_d23.vin3a_d7 */
+ { VIN2A_D22, (M5 | PIN_INPUT | MANUAL_MODE) }, /* vin2a_d22.vin3a_hsync0 */
+ { VIN2A_D23, (M5 | PIN_INPUT | MANUAL_MODE) }, /* vin2a_d23.vin3a_vsync0 */
+#endif
};
#ifdef CONFIG_IODELAY_RECALIBRATION
@@ -603,6 +651,53 @@ const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {
{0x0174, 1904, 1471}, /* CFG_GPMC_A17_IN */
{0x0188, 1690, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+#ifdef CONFIG_TARGET_DRA7XX_EVM_VISION
+ { 0x0A2C, 0, 0 }, /* CFG_VIN1B_CLK1_IN : VIN3A_CLK0 - VIP2_MANUAL2 */
+ { 0x0930, 2805, 459 }, /* CFG_VIN1A_D16_IN : VIN3A_D0 - VIP2_MANUAL2 */
+ { 0x093C, 2904, 360 }, /* CFG_VIN1A_D17_IN : VIN3A_D1 - VIP2_MANUAL2 */
+ { 0x0948, 2857, 527 }, /* CFG_VIN1A_D18_IN : VIN3A_D2 - VIP2_MANUAL2 */
+ { 0x0954, 2861, 517 }, /* CFG_VIN1A_D19_IN : VIN3A_D3 - VIP2_MANUAL2 */
+ { 0x096C, 2855, 344 }, /* CFG_VIN1A_D20_IN : VIN3A_D4 - VIP2_MANUAL2 */
+ { 0x0978, 2908, 248 }, /* CFG_VIN1A_D21_IN : VIN3A_D5 - VIP2_MANUAL2 */
+ { 0x0984, 2843, 191 }, /* CFG_VIN1A_D22_IN : VIN3A_D6 - VIP2_MANUAL2 */
+ { 0x0990, 2683, 0 }, /* CFG_VIN1A_D23_IN : VIN3A_D7 - VIP2_MANUAL2 */
+ { 0x0AEC, 1606, 0 }, /* CFG_VIN2A_D22_IN : VIN3A_HSYNC0 - VIP2_MANUAL2 */
+ { 0x0AF8, 1673, 0 }, /* CFG_VIN2A_D23_IN : VIN3A_VSYNC0 - VIP2_MANUAL2 */
+#endif
};
const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
@@ -667,6 +762,42 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {
{0x0174, 2533, 980}, /* CFG_GPMC_A17_IN */
{0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+#ifdef CONFIG_TARGET_DRA7XX_EVM_VISION
+ { 0x0930, 2244, 1202 }, /* CFG_VIN1A_D16_IN : VIN3A_D0 - VIP2_MANUAL2 */
+ { 0x093C, 2321, 1116 }, /* CFG_VIN1A_D17_IN : VIN3A_D1 - VIP2_MANUAL2 */
+ { 0x0948, 2280, 1288 }, /* CFG_VIN1A_D18_IN : VIN3A_D2 - VIP2_MANUAL2 */
+ { 0x0954, 2282, 1281 }, /* CFG_VIN1A_D19_IN : VIN3A_D3 - VIP2_MANUAL2 */
+ { 0x096C, 2284, 1090 }, /* CFG_VIN1A_D20_IN : VIN3A_D4 - VIP2_MANUAL2 */
+ { 0x0978, 2324, 1000 }, /* CFG_VIN1A_D21_IN : VIN3A_D5 - VIP2_MANUAL2 */
+ { 0x0984, 2278, 915 }, /* CFG_VIN1A_D22_IN : VIN3A_D6 - VIP2_MANUAL2 */
+ { 0x0990, 2423, 398 }, /* CFG_VIN1A_D23_IN : VIN3A_D7 - VIP2_MANUAL2 */
+ { 0x0A2C, 0, 0 }, /* CFG_VIN1B_CLK1_IN : VIN3A_CLK0 - VIP2_MANUAL2 */
+ { 0x0AEC, 1641, 0 }, /* CFG_VIN2A_D22_IN : VIN3A_HSYNC0 - VIP2_MANUAL2 */
+ { 0x0AF8, 1748, 0 }, /* CFG_VIN2A_D23_IN : VIN3A_VSYNC0 - VIP2_MANUAL2 */
+#endif
};