米6体育平台手机版

SPRACH9E November 2021 – February 2024 AWR1443 , AWR1642 , AWR1843 , AWR2544 , AWR2944 , AWR6843 , AWR6843AOP , IWR1443 , IWR1642 , IWR1843 , IWR6443 , IWR6843 , IWR6843AOP

2.2.1 Prerequisite

Refer to the device data sheet for details on the timing and interfacing requirements with the SFLASH over the QSPI interface.

SFLASH device variants should support 40-MHz operation for all commands (including normal read command). For the xWR6843 device the SFLASH device variants should support 80-MHz operation for all commands.

SFLASH supports the SFDP command and responds with JEDEC-compliant information regarding the capabilities and command set of the flash. The key fields interpreted are listed in Table 2-1.

Table 2-1 Key Fields

Field	Byte Offset
SFDP signature	[3-0]
JEDEC flash parameter offset in bytes	[0xE-0xC]
(1-1-4) Read support	[JEDEC flash parameter offset in bytes + 0x2] – bit6
(1-1-2) Read support	[JEDEC flash parameter offset in bytes + 0x2] – bit0
(1-1-4) Read command code	[JEDEC flash parameter offset in bytes + 0xB]
(1-1-4) Read dummy cycles	[JEDEC flash parameter offset in bytes + 0xA] – bit[4:0]
(1-1-2) Read command code	[JEDEC flash parameter offset in bytes + 0xD]
(1-1-2) Read dummy cycles	[JEDEC flash parameter offset in bytes + 0xC] – bit[4:0]

The number of address bytes = 3 (always).
For single data line SPI read – Read Command Code (0xB), Read Dummy cycles (8bit).