SPRACK9 February 2019 AM1705 , AM1707 , AM1806 , AM1808 , OMAP-L132 , OMAP-L137 , OMAP-L138 , TMS320C6742 , TMS320C6745 , TMS320C6746 , TMS320C6747 , TMS320C6748
When the USB PHY is powered off while still connected to a host that is powered on, the customer may notice leakage on the 3.3 V supply. This is because there is a path between VBUS and the 3.3 V supply rail that allows current to leak from the powered VBUS to the 3.3 V supply rail.
If the USB PHY remains powered off for an indefinite period of time while connected to a powered VBUS, there is a risk of long-term stress on the PHY’s internal circuitry. TI therefore recommends that customers isolate the input USB0_VBUS from the VBUS until the device is powered up. This can be accomplished by implementing a discrete load switch such as TPS22913. Some example circuits are shown in Figure 2 and Figure 3.
If the SoC supports OTG Host/Device mode:
If the SoC supports Device-only mode: