SPRACK9 February   2019 AM1705 , AM1707 , AM1806 , AM1808 , OMAP-L132 , OMAP-L137 , OMAP-L138 , TMS320C6742 , TMS320C6745 , TMS320C6746 , TMS320C6747 , TMS320C6748

 

  1.   OMAP-L13x/C674x/AM1x schematic review guidelines
    1.     Trademarks
    2. 1 Introduction
    3. 2 Recommendations Specific to OMAP-L1x/TMS320C674x/AM1x
      1. 2.1 EVM vs Data Sheet
      2. 2.2 Before You Begin
        1. 2.2.1 Documentation
        2. 2.2.2 Pinout
      3. 2.3 Critical Connections
        1. 2.3.1 Decoupling capacitors
        2. 2.3.2 Power
        3. 2.3.3 Ground
        4. 2.3.4 Clocking
        5. 2.3.5 Reset
        6. 2.3.6 Boot
        7. 2.3.7 Pin multiplexing
        8. 2.3.8 Debug
      4. 2.4 Peripherals
        1. 2.4.1 UART
        2. 2.4.2 EMAC
        3. 2.4.3 MMC/SD
        4. 2.4.4 EMIF
          1. 2.4.4.1 NAND
          2. 2.4.4.2 NOR
          3. 2.4.4.3 DDR2/mDDR
        5. 2.4.5 SPI
        6. 2.4.6 I2C
        7. 2.4.7 McASP
          1. 2.4.7.1 Audio
        8. 2.4.8 USB
          1. 2.4.8.1 USB0 (USB 2.0 OTG)
          2. 2.4.8.2 USB1 (USB 1.1 OHCI)
          3. 2.4.8.3 Unused USB pins
          4. 2.4.8.4 USB Board Design Guidelines
            1. 2.4.8.4.1 Cautionary note - USB PHY off while host is still powered on
        9. 2.4.9 Other
          1. 2.4.9.1 Signal Visibility
          2. 2.4.9.2 Voltage Level Changes
          3. 2.4.9.3 Signal Terminations
          4. 2.4.9.4 Ground Symbols
          5. 2.4.9.5 Power Symbols
    4. 3 BGA PCB Design
    5. 4 Power Management Solutions
    6. 5 References
  2.   A XDS Connector Design Checklist
    1.     A.1 XDS Connector Design
  3.   B Connecting NOR Flash to OMAP-L138
    1.     B.1 Connecting Memory Devices <32 MB
    2.     B.2 Connecting Memory Devices >32 MB

2.4.4.3 DDR2/mDDR

  • Parallel termination is not allowed on CLKP/CLKN pins.
  • If termination is used, the DDR2/mDDR drive strength should be set to full strength. Otherwise, the drive strength should be set to half strength.
  • No pullups or stubs are allowed on any DDR pins.
  • For DQS and D net classes:
    • Routes must be point-to-point.
    • Skew matching across bytes is not needed nor recommended.
    • Skew between the two classes should not exceed 25 mil.
  • Clock and DQS net class trace lengths need to be routed such that the skew between the two net classes meets the tDQSS timing parameter.

For additional guidance, see Understanding TI’s PCB routing rule-based DDR timing.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |