3.2 Address Pin Mapping

The address pin mapping between the Host and Device could vary based on the data width modes and the addressing scheme of the Host memory controllers.

A Host controller that uses the address bit 0 to represent the least significant bit of the 8-bit word address can be directly connected to the HIC address bus for 8-bit data width mode. While in case of the 16-bit data width mode, HIC_A0 has to be connected to the address bit 1 of the Host controller, since the Host address bit 1 represents a unique 16-bit word.

An example of this type of controller would be the General Purpose Memory Controller (GPMC) of the Sitara™ AM57x processor family. Table 3 shows the address translation between the GPMC and HIC for different data width modes

Some of the Host memory controllers (for example, the EMIF controller of the C2000 Device family) uses an address shifting scheme to maintain uniform memory capacity for all word sizes by supplementing the address pins with additional pins like EMxBAy. For these controllers, the Host address bit 0 represents a unique 32-bit word and, hence, the address pins of such controllers have to be connected as described in Table 4.