SPRACR2 March 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The base address configuration and the offset address to be generated by the Host varies according to the data width modes. For example, to address a region inside the Device starting from Addr[x:0], the following translation has to be used:
Where:
Table 8 captures various HICDBADDRx and I/O address offset combinations to be generated from the Host for different data width modes.
Address to be Accessed | Data Width = 16 | Data Width = 8 | ||
---|---|---|---|---|
HICDBADDRx | I/O Address Offset | HICDBADDRx | I/O Address Offset | |
0x6604 | 0x6600 | 0x4 | 0x6600 | 0x4 |
0x6688 | 0x6600 | 0x88 | 0x6680 | 0x8 |
0xFFFF0 | 0xFF00 | 0xF0 | 0xFF80 | 0x7F |