SPRACR2 March 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
As discussed in the Section 2.1, the Mailbox access mode is restricted to the HIC registers. In the Direct access mode, the Host can access both the HIC registers and the Device peripheral registers. These accesses are differentiated by the HIC_BASESEL0 pin. If an access is initiated with the HIC_BASESEL0 set to 0, it will be treated as Mailbox access operation, and if the pin is set to 1, the access will be treated as a Direct access operation.
For Direct access mode, the higher unused address pins of the Host memory controller can be connected to the HIC_BASESEL[2:0] pins and the corresponding addresses in the Host memory map can be used as the Device access offset. The Table 5 shows the BASESEL pin mapping for different access types for 16-bit data width.
| Device Signal | Host EMIF Signal | ||
|---|---|---|---|
| Mailbox Access | Direct Access | ||
| HOSTCR.PAGESEL=0 | HOSTCR.PAGESEL=1 | ||
| HIC_BASESEL0 | X (1) | EMxA7 | EMxA7 |
| HIC_BASESEL1 | X (1) | X (1) | EMxA8 |
| HIC_BASESEL2 | X (1) | X (1) | EMxA9 |