米6体育平台手机版

SPRACR2 March 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

Enabling Peripheral Expansion Applications Using the HIC
A Address Translation for Different Data Width Modes
1. A.1 Base Address and Offset Address Configuration

2.2 Data Width Selection

Support for 8-bit and 16-bit HIC data width modes is controlled via the HICMODECR.DW_MODE register field. In order to perform a 32-bit access, the Host has to initiate four accesses in 8-bit mode, while two accesses are sufficient in the case of 16-bit mode as shown in Table 1. This gives 16-bit data width mode an advantage over the 8-bit mode in terms of raw throughput at the cost of incurring 8 additional I/O pins for data.

Table 1. Host Transaction for Different Data-Width Modes

Intended Write by the Host	Data Width Mode	Write cycle1	Write cycle2	Write cycle3	Write cycle4
Address = 0x5000 Data = 0x12345678	16 bits	HICDBADDR0 = 0x5000 HIC_A[7:0] ⁽¹⁾ = 0x0 HIC_D[15:0] = 0x5678	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x1 HIC.D[15:0] = 0x1234	-	-
Address = 0x5000 Data = 0x12345678	8 bits	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x0 HIC.D[15:0] = 0x78	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x1 HIC.D[15:0] = 0x56	HICDBADDR0 = 0x5000 HIC.A[7:0] = 0x2 HIC.D[15:0] = 0x34	HICDBADDR0=0x5000 HIC.A[7:0] = 0x3 HIC.D[15:0] = 0x12

Fields in italics are I/O pins.

The address translation for different data width modes is covered in detail in Section A.