SPRACR6 April 2020 F29H850TU , F29H859TU-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1
Table 4 lists the transmission latencies for a FSI frame across 2 adjacent nodes. The transmission times for 1 data line are shown in second column and those for the 2 data line mode are shown in the third column.
| Data Size (Words)
Word = 16 Bits |
Transmission Time
1 Data Line (µSec) |
Transmission Time
2 Data Lines (µSec) |
Transmission Time
at Each Slave Mode (µSec) |
|---|---|---|---|
| 1 | 0.56 | 0.4 | 2 |
| 2 | 0.72 | 0.48 | 2 |
| 3 | 0.88 | 0.56 | 2 |
| 4 | 1.04 | 0.64 | 2 |
| 5 | 1.2 | 0.72 | 2 |
| 6 | 1.36 | 0.8 | 2 |
| 7 | 1.52 | 0.88 | 2 |
| 8 | 1.68 | 0.96 | 2 |
In addition to the above transmission delay, there may be an additional approximately 2 µs delay at each slave for receiving the data and re-transmitting the same to the adjacent slave. This is indicated in the fourth column of Table 4. This delay time is based on the current software forwarding scheme.
Now, let us consider the example of distributed power control architecture (DPCA) where 24 MPPT DC/DC boost stages, controlled by seven F28002x MCUs, are connected in a daisy chain configuration with 1 data line, with the master F2838x MCU controlling the DC/AC inverter stage. Assume that each MPPT MCU tries to send two 32-bit data variables (64-bit data), such as the MPPT voltage and current information, to the master MCU over FSI.
The worst case transmission delay in this example will be between the master MCU and the 7th MPPT DC/DC MCU. This is the one way transmission delay where data goes from the master MCU to the last DC/DC MCU in the chain or the other way.
For the 64-bit data it will take 1.04 µS for transmission between two adjacent nodes when one data line is used. In addition to this there will be approximately 2 µS delay at each MCU for forwarding the data along the chain. Therefore, the total transmission delay for data from master MCU reaching the 7th DC/DC MCU, or the other way, through the single data line will be, 7 x 1.04 µS + 6 x 2 µS = 19.28 µS.
However, the total loop delay (when data goes through the complete daisy chain loop) in transmitting and receiving data between the master MCU and any of the slave DC/DC MCUs will be the same. This delay, for one data line is, 8 x 1.04 µS + 7 x 2 µS = 22.32 µS. This means that, for this specific example of string inverter system with DPCA, any calculation done in the master MCU involving these two data variables related to any of the slave MCUs in the chain can run at a maximum frequency of about 45kHz when one data line is used. This sets the limit for the fastest calculation rate that can be off loaded to the master MCU from any of the slave MCUs in the chain or the other way. For 2 data lines the same loop delay is, 8 x 0.64 µS + 7 x 2 µS = 19.12 µS. Therefore, in this case the calculation off-loaded from one MCU to the other can run at a maximum frequency of about 52.3 kHz.