2 Clock Generator

The EPG can be used to generate clock signals. These clock signals can be used internally by the EPG (the EPG SIGGENx modules), or be exported out of the EPG through EPGOUTx signals. If exported out of the EPG through the EPGOUTx signals, then these clock signals can be used by other peripherals through the XBARs (EPGOUTs are connected to Output XBAR and CLB Output XBAR for F28003x) or be sent out of the device through GPIOs.

For example, for F28003x, EPG1 EPGOUT0 and EPGOUT1 are connected to Output XBAR. Therefore, EPGOUT0 and EPGOUT1 can be sent out of the device through GPIOs configured for Output XBAR. Also, on F28003x, the EPG1 EPGOUT2 and EPGOUT3 are connected to CLB Output XBAR, therefore; they can also be sent out of the device through GPIOs.

The EPG CLKGEN modules generate two version of output signals. The DCLK outputs are approximately 50% duty while the GCLK are the gated clocks. DCLKs can be exported out of the EPG module through EPGOUTx signals. GCLKs are used by the SIGGEN modules inside the EPG.