The SIGGEN module can operate in ROTATE RIGHT ONCE mode. This mode can be used to generate both serial data and serial clock signals. This example will generate the serial clock and serial data signals, similar to the SPI module. The SPI clock and data signals can be generated in four possible modes.

Figure 3-6 SPI Modes

All different modes of the SPICLK and SPI data can be generated by the EPG SIGGEN module. Table 3-1 maps the name of the SPICLK mode with the SPI clock polarity and phase modes.

Both the SPICLK and SPI data are generated by the SIGGEN module. The SIGGEN module will be clocked by the CLKGEN module. Similar to the previous example, the frequency of the SPICLK generated will depend on the CLKGEN period and the SIGGEN BIT-LENGTH. In this example, the CLKGEN period is set to 10 (meaning EPGCLK/10) and the BIT-LENGTH of the SIGGEN module is set 16.

With a BIT-LENGTH of 16, the SIGGEN module can generate SPICLK and SPI data signals which can output an 8-bit word on the GPIO. SIGGEN module requires a minimum BIT-LENGTH of 16 to be able place SPICLK edges between the generated SPI data. In this example, rotate right once mode is used. The same signals can be generated through the SHIFT RIGHT ONCE mode as well (explored in the next section).