SPRAD00 December   2021 DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM

 

  1.   Trademarks
  2. 1Introduction
  3. 2Jacinto 7 Display Subsystem Overview
    1. 2.1 Video (Input) Pipelines
    2. 2.2 Writeback Pipeline
    3. 2.3 Overlay Manager
    4. 2.4 Output Processing
    5. 2.5 Output Display Interfaces
      1. 2.5.1 Embedded Display Port (eDP)
      2. 2.5.2 MIPI Display Serial Interface (DSI)
      3. 2.5.3 Display Parallel Interface (DPI)
    6. 2.6 Safety Support
  4. 3Display Subsystem Use-case Examples
    1. 3.1 3-Display Configuration
  5. 4TDA4VM/DRA829V Hardware Display Support
  6. 5 Display Subsystem Software Architecture
    1. 5.1 Linux DSS Architecture
    2. 5.2 QNX Software Architecture
    3. 5.3 RTOS-Based DSS Support
  7. 6References

2.5.2 MIPI Display Serial Interface (DSI)

  • Compliance with MIPI DSI v1.3.1 protocol specification and previous specifications
  • Programmable display resolutions with maximum clock rate not exceeding the total available bandwidth over 4MPix @60fps
    • Supporting resolutions up to 2560x1440 @60fps (2.5K)
  • The MIPI DSI (Physical Layer) D-PHY module supports:
    • Compliance with MIPI D-PHY 1.2 physical layer interface specification and features
    • 1, 2 or 4 data lanes, in addition to clock signaling
    • Maximum data rate up to 2.5 Gbps per data lane
  • It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single-link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes)
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