Special branch instructions allow the C29 compiler to collapse multiple branch destinations into a single instruction. switch is a common construct that occurs in general purpose code, such as housekeeping tasks. The C29 ISA has multiway branch instructions QDECB and DDECB that allow very efficient implementation. In quad decrement branch (QDECB), four destinations are allowed, with the fifth option being linear execution. In dual decrement branch (DDECB), two destinations are allowed, and the third option is linear execution.

A 16 case switch statement is illustrated in the code block below. On the C29 CPU, the switch is implemented with one branch instruction (BCMP) and four QDECB instructions, taking 10 to 17 cycles, depending on the input. On the Cortex-M7, the switch is implemented with compare and branch instructions for each case, thus taking 6 to 51 cycles, depending on the input.

switch(state) { case 15: .... break; case 14: .... break; case 13: .... break; ... ... case 0: .... break; default: .... break; }  

C29 Implementation
LD.32 A14,@State  
BCMP @default,A.GT,A14,#15   QDECBA14,#0x4,@case15,@Case14,@Case13,@Case12,@  QDECBA14,#0x4,@case11,@Case10,@Case9,@Case8,@   QDECBA14,#0x2,@case7,@case6,@case5,@case4,@  
QDECBA14,#0x2,@case3,@case2,@case1,@case0,@  
default:
.... 
.... 
LB @State_end
case15:
.... 
.... 
LB @State_end 
case14:
.... 
.... 
LB @State_end 
case13:
.... 
.... 
LB @State_end 
....
....
....
case2: 
.... 
.... 
LB @State_end 
case1: 
.... 
.... 
LB @State_end 
case0: 
.... 
.... 
State_end:

M7 Implementation
LDRSB R6,[State]
CMP   R6,#15  
BGT.N default  
BEQ.N case15  
CMP   R6,#14  
BEQ.N case14  
.... 
CMP   R6,#0  
BEQ.N case0   
default:
.... 
.... 
B  State_end 
case15:
.... 
.... 
B  State_end 
case14:
.... 
.... 
B  State_end 
case13:
.... 
.... 
B  State_end 
....
....
....
case2: 
.... 
.... 
B  State_end 
case1: 
.... 
.... 
B  State_end 
case0: 
.... 
.... 
State_end: