2 C29 CPU and Key Features

Figure 2-1 shows the block diagram of the C29 CPU, and its key features and benefits are highlighted below.

Figure 2-1 C29 Architecture Block Diagram

VLIW CPU: The C29 is based on a Very Long Instruction Word (VLIW) architecture. Variable size instructions (16-bit, 32-bit, and 48-bit) are supported. The size of the instruction packet can be 16-bit to 128-bits, thus enabling better code density, as well as up to eight 16-bit instructions that are executed in a single CPU cycle.

CPU Memory Bus: A 128-bit wide program bus can fetch a 128-bit wide instruction packet for the CPU to execute. Two 64-bit read buses enable parallel reads of 64-bits, and a 64-bit write bus enables writing 64-bit data to memory, all in a single cycle.

Byte addressability and Data Types: The C29 supports byte addressing, with data types fully compatible with other popular CPU architectures such as ARM.

CPU Registers: There are three sets of registers; Ax, Dx, and Mx. Ax registers (16 32-bit registers A0-A15 or eight 64-bit registers XA0-XA14) are primarily meant for address generation. Additionally, certain integer operations are executed in the early phase of pipeline for improved performance. Dx registers (16 32-bit registers D0-D15 or eight 64-bit registers XD0-XD14) are meant for integer fixed-point operations and Mx registers (32 32-bit registers M0-M31 or 16 64-bit registers XM0-XM30) are for floating-point operations.

Functional Units: There are a total of 24 functional units associated with register sets Ax, Dx, and Mx, and special function registers. Each functional unit supports a set of instructions. Certain functional units have multiple instances. As an example, there are four compare units associated with the Ax register file that evaluate two cases of a switch statement every cycle that improves switch statement execution. There are two floating-point multiply and three floating-point add or subtract units associated with the Mx register set that execute one FFT butterfly every two cycles.

Trigonometric Math Unit (TMU): Trigonometric operations are supported and extended for a 64-bit dual precision floating-point, in addition to a 32-bit single precision floating-point.

Interrupts: The C29 supports regular interrupts (termed INT) and an optimized interrupt called real-time interrupt (RTINT). RTINT uses a dedicated hardware interrupt stack. When an RTINT occurs, CPU context is saved off automatically to this stack, which is faster than a software based context save mechanism). In addition to being faster, it is also a fixed number of cycles - thus improving determinism - whereas a software based context save mechanism can take a variable number of cycles. Hardware interrupt prioritization is supported to reduce software overhead of prioritization through software.

Safety: Higher ASIL levels requires code isolation among multiple threads running within or across CPUs. The Safety and Security Unit (SSU) enables isolation among these threads. In a simplistic form, SSU allows a user to define multiple associated memory regions (called Access Protected Regions (APR)) that can be tied together (through a concept known as a LINK) to create an isolated thread. A thread consists of code, data, a stack, and peripherals. A specific code LINK can access specific data LINKs through Read, Write, or both Read and Write permissions. The advantage of SSU over a traditional MPU is that permissions are enforced based on code being executed. As a result, there is no need to reprogram the MPU. Each thread has a hardware STACK and STACKs are switched automatically in the CPU to enable full isolation. In an OS context - AUTOSAR for example - this efficient switching allows real-time ISRs to be CAT1 interrupts unaffected by the OS, and be completely isolated from the AUTOSAR application. Thus, a single C29 CPU core can run an OS and control tasks without affecting control performance.

Security: When code execution moves across STACKs, entry and exit points are enforced. Entry and exit points are well-defined points where one thread calls or branches into, or returns from, another thread. Calling, branching to, or returning from any other address creates an exception, therefore avoiding security attacks. The SSU also supports firmware updates and debug through a mechanism called ZONEs, with each ZONE having independent password and debug settings. ZONEs enable secure multiparty development, where each party defines a password to block code visibility and controls code debug by another party.