Software pipelining of loops allows multiple iterations of loops to execute in parallel, leveraging the VLIW architecture of the C29 CPU. In Figure 3-7, software pipelining is illustrated for the CFFT. The assembly is hand-written, where the complete 128-bit instruction packet is used and 8 instructions are executed in parallel per cycle in the loop.

Figure 3-7 Software Pipelining in CFFT - Handwritten Assembly.

With -O3 optimization, the C29 compiler generates software pipelined loops, as shown in Figure 3-8, for the FIR. Software pipelining allows loops to perform faster.

Figure 3-8 Software Pipelining in FIR - Compiler Generated.