SPRADD8 November   2024 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to Real-Time Control
  5. 2C29 CPU and Key Features
    1. 2.1 Parallel Architecture and Compiler Entitlement
  6. 3C29 Performance Benchmarks
    1. 3.1 Signal Chain Benchmark with ACI Motor Control
    2. 3.2 Real-time Control and DSP Performance
      1. 3.2.1 Examples and Factors Contributing to Results
        1. 3.2.1.1 Saturation (or Limiting) Example
        2. 3.2.1.2 Dead Zone Example
        3. 3.2.1.3 Space Vector Generation (SVGEN) Example
        4. 3.2.1.4 Software Pipelining
      2. 3.2.2 Customer Control and Math Benchmarks
    3. 3.3 General Purpose Processing (GPP) Performance
      1. 3.3.1 Examples and Factors Contributing to Results
        1. 3.3.1.1 Discontinuity Management
        2. 3.3.1.2 Switch() Example
    4. 3.4 Model-Based Design Benchmarks
    5. 3.5 Application Benchmarks
      1. 3.5.1 Single Phase 7kW OBC Description
      2. 3.5.2 Vienna Rectifier-Based Three Phase Power Factor Correction
      3. 3.5.3 Single-Phase Inverter
      4. 3.5.4 Machine Learning
    6. 3.6 Flash Memory Efficiency
    7. 3.7 Code-size Efficiency
  7. 4Summary
  8. 5References

Code-size Efficiency

In addition to performance efficiency, code-size efficiency is an important metric, especially when zero wait-state memory is limited. Performance critical code is usually run out of zero wait-state memory, and non performance critical code is run from Flash memory. Code-size Benchmarks shows code-size efficiency of various benchmarks, comparing C29 with C28 and ARM (Cortex-M7). A few points are noted from the results:

  • C29 code-size is mostly comparable to C28, as well as Cortex-M7 code-size. In some benchmarks, the C29 achieves lower code-size, and in some other benchmarks higher code-size.
  • Code-size results correspond to the -O3 optimization setting of the compiler. The user has the flexibility to selectively use -Oz on portions of code to reduce code-size.
  • C29 FIR code-size is larger because of software pipelining (which results in a huge performance boost). Loops, in general, are a small part of overall code.
Table 3-7 Code-size Benchmarks
DSP, Math, and Real-time BenchmarksC28 versus C29 code-size (C) <1 implies C28 code-size is smallerCortex-M7 vs C29 code-size (C) <1 implies Cortex-M7 code-size is smaller
FIR0.50.7
IIR0.71.4
DCL (Digital Control Library)1.51.5
FCL (Fast Current Loop)1.11.1
SPLL (Software Phase Locked Loop)1.71.2
SVGEN1.21
ACI signal chain0.90.6
Customer DSP, Math, and Real-time Benchmarks
B_Interp1.11
C_Motor1.31
D_Math0.80.8
E_Math10.7
GPP Benchmarks
F_GPP0.80.8
G_GPP0.70.7
Reference designs
Vienna Rectifier0.94
Single-phase inverter0.75