TIDM-2013 is a reference design built using the F28x family of devices to implement single phase OBC design. The design consists of an interleaved continuous conduction mode (CCM) totem-pole (TTPL) bridgeless power-factor correction (PFC) power stage followed by a CLLLC DCDC power stage. The design runs the following ISRs at the mentioned frequencies:

• ISR1 (PWM Update): 120KHz
• ISR2 (PFC Current, CLLC Voltage Loop): 120KHz
• ISR3 (PFC Voltage Loop + Instrumentation): 10KHz

Figure 3-13 shows benchmarks for the above ISRs comparing F29x versus F28x running at the same CPU clock frequency of 200MHz. ISR1 does not change between F29x and F28x because the primary operations in it are PWM peripheral register writes, which do not change between F28x and F29x. ISR2 on F29x is 1.7 times faster compared to F28x.

Figure 3-13 OBC Benchmark