The assembler detects certain pipeline conflicts, and based on their severity, issues either an error message or a warning. The types of pipeline conflicts detected are listed below, along with the assembler actions in the event of each conflict.

• Pipeline Conflict:

  An instruction reads a register when it is being written by another instruction.

  Assembler Response:

  The assembler generates an error message and aborts.

• Pipeline Conflict:

  Two instructions write the same register in the same cycle.

  Assembler Response:

  The assembler generates an error message and aborts.

• Pipeline Conflict:

  Instructions FRACF32, I16TOF32, UI16TOF32, F32TOI32, and/or F32TOUI32 are present in the delay slot of a specific type of MOV32 instruction that moves a value from a CPU register or memory location to an FPU register.

  Assembler Response:

  The assembler gives an error message and aborts, as the hardware is not able to correctly execute this sequence.

• Pipeline Conflict:

  Parallel operations have the same destination register.

  Assembler Response:

  The assembler gives a warning.

• Pipeline Conflict:

  A read/write happens in the delay slot of a write of the same register.

  Assembler Response:

  The assembler gives a warning.

• Pipeline Conflict:

  A SAVE operation happens in the delay slot of a pipeline operation.

  Assembler Response:

  The assembler gives a warning.

• Pipeline Conflict:

  A RESTORE operation happens in the delay slot of a pipeline operation.

  Assembler Response:

  The assembler gives a warning.

• Pipeline Conflict:

  A SETFLG instruction tries to modify the LUF or LVF flag while certain instructions that modify LUF/LVF (such as ADDF32, SUBF32, EINVF32, EISQRTF32 etc) have pending writes.

  Assembler Response:

  The assembler does not check for which instructions have pending writes; on encountering a SETFLG when any write is pending, the assembler issues a detailed warning, asking you to ensure that the SETFLG is not in the delay slot of the specified instructions.

For the actual timing of each FPU instruction, and pipeline modeling, please refer to the TMS320C28x Floating Point Unit and Instruction Set Reference Guide. Timing information for VCU instructions can be found in the TMS320x28xx, 28xxx DSP Peripherals Reference Guide.