SPRUHM8K December 2013 – May 2024 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28378D , TMS320F28379D , TMS320F28379D-Q1
This event occurs when the DMA channel descriptors are programmed while the PEND bit in the uPP DMA channel status register is set to 1. A channel’s descriptors must only be programmed while the channel's PEND bit is cleared to 0.