There are two different SDRAM configuration
procedures. Although the EMIF automatically performs the SDRAM initialization
sequence described in Section 25.2.5.4 when coming out of reset, follow one of the procedures before performing any EMIF
memory requests.
Procedure A must be followed if the SDRAM power-up
constraint was not violated during the SDRAM auto-initialization sequence detailed
in Section 25.2.5.4 on coming out of Reset. The SDRAM power-up constraint specifies that 200μs
(sometimes 100μs) must exist between receiving stable Vdd and CLK and the issuing of
a PRE command.
Procedure B must be followed if the SDRAM power-up
constraint was violated. The 200μs (100μs) SDRAM power-up constraint is violated, if
the frequency of EM1CLK is greater than 50MHz (100MHz for 100μs SDRAM power-up
constraint) during SDRAM Auto-Initialization Sequence. Procedure B must be followed
if there is any doubt that the power-up constraint was not met.
Procedure A — Following is the procedure to
be followed if the SDRAM power-up constraint was not violated:
- Place the SDRAM into self-refresh mode by setting
the SR bit of SDRAM_CR to 1. The SDRAM can be placed into self-refresh mode
when changing the frequency of the EM1CLK to avoid incurring the 200μs
power-up constraint again.
- Configure the desired EMIF1 clock (EM1CLK)
frequency. The frequency of the memory clock must meet the timing
requirements in the SDRAM manufacturer's documentation and the timing
limitations shown in the electrical specifications of the device data
sheet.
- Remove the SDRAM from self-refresh mode by clearing the SR bit of the SDRAM_CR to 0.
- Program SDRAM_TR and SDR_EXT_TMNG to satisfy the timing requirements for the attached SDRAM device. The timing parameters must be taken from the SDRAM data sheet.
- Program the RR field of SDRAM_RCR to match that
of the attached device's refresh interval. See Section 25.2.5.6.1 details on determining the appropriate value.
- Program the SDRAM_CR to match the characteristics
of the attached SDRAM device. This causes the auto-initialization sequence
in Section 25.2.5.4 to be re-run. This second initialization generally takes much less time
due to the increased frequency of EM1CLK.
Procedure B — Following is the procedure to be followed if the SDRAM power-up constraint was violated:
- Configure the desired EM1CLK clock frequency. The
frequency of the memory clock must meet the timing requirements in the SDRAM
manufacturer's documentation and the timing limitations shown in the
electrical specifications of the device data sheet.
- Program SDRAM_TR and SDR_EXT_TMNG to satisfy the timing requirements for the attached SDRAM device. The timing parameters must be taken from the SDRAM data sheet.
- Program the RR field of the SDRAM_RCR such that
the following equation is satisfied:
(RR × 8)/(fEM1CLK) > 200μs (sometimes
100μs). For example, an EM1CLK frequency of 100MHz requires setting RR
to 2501 (9C5h) or higher to meet a 200μs
constraint.
- Program the SDRAM_CR to match the characteristics
of the attached SDRAM device. This causes the auto-initialization sequence
in Section 25.2.5.4 to be re-run with the new value of RR.
- Perform a read from the SDRAM to make sure that
step 5 of this procedure occurs after the initialization process has
completed. Alternatively, wait for 200μs instead of performing a read.
- Finally, program the RR field to match that of
the attached device's refresh interval. See Section 25.2.5.6.1 details on determining the appropriate value.
After following the above procedure, the EMIF is ready to perform accesses to the attached SDRAM device.