The uPP internal DMA controller uses a simplified programming model similar to 2D transfers performed by any other DMA at system level. Each DMA channel may be configured with four parameters: window address, byte count, line count, and line offset address.

• Window Address (CHxDESC0.ADDR) - The location in uPP data memory of the first byte in the data buffer. When the uPP operates in receive mode, the DMA channel begins writing to this address as it takes incoming data from the uPP I/O channel. When the uPP operates in transmit mode, the DMA channel begins reading from this address and pass the data to the uPP I/O channel. The window address must be aligned to a 64-bit boundary (that is, the three LSBs must equal 0). Non-aligned addresses are automatically adjusted to a properly aligned value when written to configuration register.
• Byte Count (CHxDESC1.BCNT) - The number of bytes per line. The byte count must be an even number.
• Line Count (UPxDESC1.LCNT) - The number of lines per window. The total number of bytes transferred equals B x L, where B is the byte count per line and L is the line count.
• Line Offset Address (CHxDESC2.LOFFSET) - The offset address between the first byte in successive Lines. The line offset address cannot exceed 65528 (FFF8h) bytes, and must be aligned to a 64-bit boundary in memory (that is, the three LSBs must equal 0).

Figure 24-9 shows a typical DMA window defined by these parameters.

Figure 24-9 Structure of DMA Window and Lines in Memory

Certain values of the line offset address have special implications on the structure of the data buffer:

• Line Offset Address = Byte Count : Data buffer is a contiguous block in memory with size equal to (Line Count) x (Byte Count).
• Line Offset Address = 0 : Data buffer consists of a single line, with total size equal to Byte Count. If the I/O channel is configured in transmit mode, this line is transmitted (Line Count) consecutive times before the DMA transfer completes. If the I/O channel is configured in receive mode, the buffer is repeatedly written and overwritten by incoming data.

To program a DMA transfer, write the appropriate fields in the DMA channel descriptor registers for DMA Channel I or for DMA Channel Q. If the associated I/O channel is initialized and idle, the DMA transfer and I/O transaction begins immediately. Section 24.4.10 describes a step-by-step process for configuring the I/O channel and DMA channels to start a uPP transfer.

Each DMA channel allows a second descriptor to be queued while the previously programmed DMA transfer is still running. The PEND status bit in channel status register reports whether a new set of DMA parameters may be written to the DMA descriptor registers. Each DMA channel can have at most one active transfer and one queued transfer. This allows each I/O channel to perform uninterrupted, consecutive transactions across DMA transfer boundaries.

This DMA controller does not support automatically reloading DMA transfer descriptors. Each successive descriptor set must be explicitly written to the configuration registers by software. All uPP interrupt events originate in the internal DMA controller. Section 24.4.6 lists and explains all uPP interrupt events.

The internal DMA controller always writes data in bursts of 64 bytes. However, DMA read operations have configurable burst size, which may be set per channel using the RDSIZEI and RDSIZEQ bits in the uPP threshold configuration register. A DMA channel waits until the specified number of bytes leaves its internal buffer before performing another burst read from memory.

Note that the TXSIZEA bit in threshold configuration register is not DMA parameters; instead, it control transmit thresholds for the uPP interface channel.