米6体育平台手机版

SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

1
Read This First
1. About This Manual
2. Notational Conventions
3. Glossary
4. Related Documentation From Texas Instruments
5. Support Resources
6. Trademarks
1 C2000™ Microcontrollers Software Support
1. 1.1 Introduction
2. 1.2 C2000Ware Structure
3. 1.3 Documentation
4. 1.4 Devices
5. 1.5 Libraries
6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
7. 1.7 SysConfig and PinMUX Tool
2 C28x Processor
1. 2.1 Introduction
2. 2.2 C28X Related Collateral
3. 2.3 Features
4. 2.4 Floating-Point Unit
5. 2.5 Trigonometric Math Unit (TMU)
3 System Control and Interrupt
1. 3.1 Introduction
2. 3.2 System Control Functional Description
  1. 3.2.1 Device Identification
  2. 3.2.2 Device Configuration Registers
3. 3.3 Resets
4. 3.4 Peripheral Interrupts
5. 3.5 Exceptions and Non-Maskable Interrupts
6. 3.6 Safety Features
7. 3.7 Clocking
8. 3.8 32-Bit CPU Timers 0/1/2
9. 3.9 Watchdog Timers
10. 3.10 Low-Power Modes
11. 3.11 Memory Controller Module
  1. 3.11.1 Functional Description
12. 3.12 Flash and OTP Memory
13. 3.13 Dual Code Security Module (DCSM)
14. 3.14 JTAG
15. 3.15 System Control Register Configuration Restrictions
16. 3.16 Software
17. 3.17 System Control Registers
4 ROM Code and Peripheral Booting
1. 4.1 Introduction
2. 4.2 Boot ROM Registers
3. 4.3 Device Boot Sequence
4. 4.4 Device Boot Modes
5. 4.5 Configuring Boot Mode Pins
6. 4.6 Configuring Get Boot Options
7. 4.7 Configuring Emulation Boot Options
8. 4.8 Device Boot Flow Diagrams
  1. 4.8.1 Emulation Boot Flow Diagrams
  2. 4.8.2 Standalone and Hibernate Boot Flow Diagrams
9. 4.9 Device Reset and Exception Handling
  1. 4.9.1 Reset Causes and Handling
  2. 4.9.2 Exceptions and Interrupts Handling
10. 4.10 Boot ROM Description
5 Direct Memory Access (DMA)
1. 5.1 Introduction
  1. 5.1.1 Features
  2. 5.1.2 Block Diagram
2. 5.2 Architecture
3. 5.3 Address Pointer and Transfer Control
4. 5.4 Pipeline Timing and Throughput
5. 5.5 CPU and CLA Arbitration
6. 5.6 Channel Priority
  1. 5.6.1 Round-Robin Mode
  2. 5.6.2 Channel 1 High-Priority Mode
7. 5.7 Overrun Detection Feature
8. 5.8 Software
  1. 5.8.1 DMA Examples
9. 5.9 DMA Registers
6 Control Law Accelerator (CLA)
1. 6.1 Introduction
2. 6.2 CLA Interface
3. 6.3 CLA and CPU Arbitration
4. 6.4 CLA Configuration and Debug
5. 6.5 Pipeline
6. 6.6 Software
  1. 6.6.1 CLA Examples
    1. 6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
    2. 6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
7. 6.7 Instruction Set
  1. 6.7.1 Instruction Descriptions
  2. 6.7.2 Addressing Modes and Encoding
  3. 6.7.3 Instructions
    1. MABSF32 MRa, MRb
    2. MADD32 MRa, MRb, MRc
    3. MADDF32 MRa, #16FHi, MRb
    4. MADDF32 MRa, MRb, #16FHi
    5. MADDF32 MRa, MRb, MRc
    6. MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
    7. MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    8. MAND32 MRa, MRb, MRc
    9. MASR32 MRa, #SHIFT
    10. MBCNDD 16BitDest [, CNDF]
    11. MCCNDD 16BitDest [, CNDF]
    12. MCMP32 MRa, MRb
    13. MCMPF32 MRa, MRb
    14. MCMPF32 MRa, #16FHi
    15. MDEBUGSTOP
    16. MEALLOW
    17. MEDIS
    18. MEINVF32 MRa, MRb
    19. MEISQRTF32 MRa, MRb
    20. MF32TOI16 MRa, MRb
    21. MF32TOI16R MRa, MRb
    22. MF32TOI32 MRa, MRb
    23. MF32TOUI16 MRa, MRb
    24. MF32TOUI16R MRa, MRb
    25. MF32TOUI32 MRa, MRb
    26. MFRACF32 MRa, MRb
    27. MI16TOF32 MRa, MRb
    28. MI16TOF32 MRa, mem16
    29. MI32TOF32 MRa, mem32
    30. MI32TOF32 MRa, MRb
    31. MLSL32 MRa, #SHIFT
    32. MLSR32 MRa, #SHIFT
    33. MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
    34. MMAXF32 MRa, MRb
    35. MMAXF32 MRa, #16FHi
    36. MMINF32 MRa, MRb
    37. MMINF32 MRa, #16FHi
    38. MMOV16 MARx, MRa, #16I
    39. MMOV16 MARx, mem16
    40. MMOV16 mem16, MARx
    41. MMOV16 mem16, MRa
    42. MMOV32 mem32, MRa
    43. MMOV32 mem32, MSTF
    44. MMOV32 MRa, mem32 [, CNDF]
    45. MMOV32 MRa, MRb [, CNDF]
    46. MMOV32 MSTF, mem32
    47. MMOVD32 MRa, mem32
    48. MMOVF32 MRa, #32F
    49. MMOVI16 MARx, #16I
    50. MMOVI32 MRa, #32FHex
    51. MMOVIZ MRa, #16FHi
    52. MMOVZ16 MRa, mem16
    53. MMOVXI MRa, #16FLoHex
    54. MMPYF32 MRa, MRb, MRc
    55. MMPYF32 MRa, #16FHi, MRb
    56. MMPYF32 MRa, MRb, #16FHi
    57. MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
    58. MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    59. MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    60. MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
    61. MNEGF32 MRa, MRb[, CNDF]
    62. MNOP
    63. MOR32 MRa, MRb, MRc
    64. MRCNDD [CNDF]
    65. MSETFLG FLAG, VALUE
    66. MSTOP
    67. MSUB32 MRa, MRb, MRc
    68. MSUBF32 MRa, MRb, MRc
    69. MSUBF32 MRa, #16FHi, MRb
    70. MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
    71. MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
    72. MSWAPF MRa, MRb [, CNDF]
    73. MTESTTF CNDF
    74. MUI16TOF32 MRa, mem16
    75. MUI16TOF32 MRa, MRb
    76. MUI32TOF32 MRa, mem32
    77. MUI32TOF32 MRa, MRb
    78. MXOR32 MRa, MRb, MRc
8. 6.8 CLA Registers
7 General-Purpose Input/Output (GPIO)
1. 7.1 Introduction
  1. 7.1.1 GPIO Related Collateral
2. 7.2 Configuration Overview
3. 7.3 Digital General-Purpose I/O Control
4. 7.4 Input Qualification
5. 7.5 USB Signals
6. 7.6 SPI Signals
7. 7.7 GPIO and Peripheral Muxing
  1. 7.7.1 GPIO Muxing
  2. 7.7.2 Peripheral Muxing
8. 7.8 Internal Pullup Configuration Requirements
9. 7.9 Software
  1. 7.9.1 GPIO Examples
  2. 7.9.2 LED Examples
10. 7.10 GPIO Registers
8 Crossbar (X-BAR)
1. 8.1 Input X-BAR
2. 8.2 ePWM, CLB, and GPIO Output X-BAR
3. 8.3 XBAR Registers
9 Analog Subsystem
1. 9.1 Introduction
  1. 9.1.1 Features
  2. 9.1.2 Block Diagram
2. 9.2 Optimizing Power-Up Time
3. 9.3 Analog Subsystem Registers
  1. 9.3.1 Analog Subsystem Base Addresses
  2. 9.3.2 ANALOG_SUBSYS_REGS Registers
10Analog-to-Digital Converter (ADC)
1. 10.1 Introduction
2. 10.2 ADC Configurability
3. 10.3 SOC Principle of Operation
4. 10.4 SOC Configuration Examples
5. 10.5 ADC Conversion Priority
6. 10.6 Burst Mode
  1. 10.6.1 Burst Mode Example
  2. 10.6.2 Burst Mode Priority Example
7. 10.7 EOC and Interrupt Operation
8. 10.8 Post-Processing Blocks
9. 10.9 Opens/Shorts Detection Circuit (OSDETECT)
10. 10.10 Power-Up Sequence
11. 10.11 ADC Calibration
  1. 10.11.1 ADC Zero Offset Calibration
12. 10.12 ADC Timings
  1. 10.12.1 ADC Timing Diagrams
13. 10.13 Additional Information
14. 10.14 Software
  1. 10.14.1 ADC Examples
15. 10.15 ADC Registers
11Buffered Digital-to-Analog Converter (DAC)
1. 11.1 Introduction
2. 11.2 Using the DAC
3. 11.3 Lock Registers
4. 11.4 Software
  1. 11.4.1 DAC Examples
5. 11.5 DAC Registers
12Comparator Subsystem (CMPSS)
1. 12.1 Introduction
2. 12.2 Comparator
3. 12.3 Reference DAC
4. 12.4 Ramp Generator
5. 12.5 Digital Filter
  1. 12.5.1 Filter Initialization Sequence
6. 12.6 Using the CMPSS
7. 12.7 Software
  1. 12.7.1 CMPSS Examples
    1. 12.7.1.1 CMPSS Asynchronous Trip
    2. 12.7.1.2 CMPSS Digital Filter Configuration
8. 12.8 CMPSS Registers
13Sigma Delta Filter Module (SDFM)
1. 13.1 Introduction
2. 13.2 Configuring Device Pins
3. 13.3 Input Control Unit
4. 13.4 Sinc Filter
  1. 13.4.1 Data Rate and Latency of the Sinc Filter
5. 13.5 Data (Primary) Filter Unit
  1. 13.5.1 32-bit or 16-bit Data Filter Output Representation
  2. 13.5.2 SDSYNC Event
6. 13.6 Comparator (Secondary) Filter Unit
  1. 13.6.1 Higher Threshold (HLT) Comparator
  2. 13.6.2 Lower Threshold (LLT) Comparator
7. 13.7 Theoretical SDFM Filter Output
8. 13.8 Interrupt Unit
  1. 13.8.1 SDFM (SDINT) Interrupt Sources
9. 13.9 Register Descriptions
10. 13.10 Software
  1. 13.10.1 SDFM Examples
11. 13.11 SDFM Registers
14Enhanced Pulse Width Modulator (ePWM)
1. 14.1 Introduction
  1. 14.1.1 EPWM Related Collateral
  2. 14.1.2 Submodule Overview
2. 14.2 Configuring Device Pins
3. 14.3 ePWM Modules Overview
4. 14.4 Time-Base (TB) Submodule
5. 14.5 Counter-Compare (CC) Submodule
6. 14.6 Action-Qualifier (AQ) Submodule
7. 14.7 Dead-Band Generator (DB) Submodule
8. 14.8 PWM Chopper (PC) Submodule
9. 14.9 Trip-Zone (TZ) Submodule
10. 14.10 Event-Trigger (ET) Submodule
  1. 14.10.1 Operational Overview of the ePWM Event-Trigger Submodule
11. 14.11 Digital Compare (DC) Submodule
12. 14.12 ePWM Crossbar (X-BAR)
13. 14.13 Applications to Power Topologies
14. 14.14 High-Resolution Pulse Width Modulator (HRPWM)
  1. 14.14.1 Operational Description of HRPWM
  2. 14.14.2 SFO Library Software - SFO_TI_Build_V8.lib
    1. 14.14.2.1 Scale Factor Optimizer Function - int SFO()
    2. 14.14.2.2 Software Usage
      1. 14.14.2.2.1 A Sample of How to Add "Include" Files
      2. 730
      3. 14.14.2.2.2 Declaring an Element
      4. 732
      5. 14.14.2.2.3 Initializing With a Scale Factor Value
      6. 734
      7. 14.14.2.2.4 SFO Function Calls
15. 14.15 ePWM Registers
15Enhanced Capture (eCAP)
1. 15.1 Introduction
  1. 15.1.1 Features
  2. 15.1.2 ECAP Related Collateral
2. 15.2 Description
3. 15.3 Configuring Device Pins for the eCAP
4. 15.4 Capture and APWM Operating Mode
5. 15.5 Capture Mode Description
6. 15.6 Application of the eCAP Module
7. 15.7 Application of the APWM Mode
  1. 15.7.1 Example 1 - Simple PWM Generation (Independent Channels)
8. 15.8 Software
  1. 15.8.1 ECAP Examples
9. 15.9 eCAP Registers
16Enhanced Quadrature Encoder Pulse (eQEP)
1. 16.1 Introduction
  1. 16.1.1 EQEP Related Collateral
2. 16.2 Configuring Device Pins
3. 16.3 Description
4. 16.4 Quadrature Decoder Unit (QDU)
5. 16.5 Position Counter and Control Unit (PCCU)
6. 16.6 eQEP Edge Capture Unit
7. 16.7 eQEP Watchdog
8. 16.8 eQEP Unit Timer Base
9. 16.9 eQEP Interrupt Structure
10. 16.10 eQEP Registers
17Serial Peripheral Interface (SPI)
1. 17.1 Introduction
2. 17.2 System-Level Integration
3. 17.3 SPI Operation
4. 17.4 Programming Procedure
5. 17.5 Software
  1. 17.5.1 SPI Examples
6. 17.6 SPI Registers
18Serial Communications Interface (SCI)
1. 18.1 Introduction
2. 18.2 Architecture
3. 18.3 SCI Module Signal Summary
4. 18.4 Configuring Device Pins
5. 18.5 Multiprocessor and Asynchronous Communication Modes
6. 18.6 SCI Programmable Data Format
7. 18.7 SCI Multiprocessor Communication
8. 18.8 Idle-Line Multiprocessor Mode
9. 18.9 Address-Bit Multiprocessor Mode
  1. 18.9.1 Sending an Address
10. 18.10 SCI Communication Format
  1. 18.10.1 Receiver Signals in Communication Modes
  2. 18.10.2 Transmitter Signals in Communication Modes
11. 18.11 SCI Port Interrupts
  1. 18.11.1 Break Detect
12. 18.12 SCI Baud Rate Calculations
13. 18.13 SCI Enhanced Features
14. 18.14 Software
  1. 18.14.1 SCI Examples
15. 18.15 SCI Registers
19Inter-Integrated Circuit Module (I2C)
1. 19.1 Introduction
2. 19.2 Configuring Device Pins
3. 19.3 I2C Module Operational Details
4. 19.4 Interrupt Requests Generated by the I2C Module
  1. 19.4.1 Basic I2C Interrupt Requests
  2. 19.4.2 I2C FIFO Interrupts
5. 19.5 Resetting or Disabling the I2C Module
6. 19.6 Software
  1. 19.6.1 I2C Examples
7. 19.7 I2C Registers
20Multichannel Buffered Serial Port (McBSP)
1. 20.1 Introduction
2. 20.2 Configuring Device Pins
3. 20.3 McBSP Operation
4. 20.4 McBSP Sample Rate Generator
5. 20.5 McBSP Exception/Error Conditions
6. 20.6 Multichannel Selection Modes
7. 20.7 SPI Operation Using the Clock Stop Mode
8. 20.8 Receiver Configuration
9. 20.9 Transmitter Configuration
10. 20.10 Emulation and Reset Considerations
  1. 20.10.1 McBSP Emulation Mode
  2. 20.10.2 Resetting and Initializing McBSPs
11. 20.11 Data Packing Examples
  1. 20.11.1 Data Packing Using Frame Length and Word Length
  2. 20.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
12. 20.12 Interrupt Generation
13. 20.13 McBSP Modes
14. 20.14 Special Case: External Device is the Transmit Frame Master
15. 20.15 Software
  1. 20.15.1 MCBSP Examples
16. 20.16 McBSP Registers
21Controller Area Network (CAN)
1. 21.1 Introduction
2. 21.2 Functional Description
  1. 21.2.1 Configuring Device Pins
  2. 21.2.2 Address/Data Bus Bridge
3. 21.3 Operating Modes
4. 21.4 Multiple Clock Source
5. 21.5 Interrupt Functionality
6. 21.6 Parity Check Mechanism
  1. 21.6.1 Behavior on Parity Error
7. 21.7 Debug Mode
8. 21.8 Module Initialization
9. 21.9 Configuration of Message Objects
10. 21.10 Message Handling
11. 21.11 CAN Bit Timing
  1. 21.11.1 Bit Time and Bit Rate
  2. 21.11.2 Configuration of the CAN Bit Timing
12. 21.12 Message Interface Register Sets
  1. 21.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
  2. 21.12.2 Message Interface Register Set 3 (IF3)
13. 21.13 Message RAM
14. 21.14 Software
  1. 21.14.1 CAN Examples
15. 21.15 CAN Registers
22Universal Serial Bus (USB) Controller
1. 22.1 Introduction
2. 22.2 Functional Description
3. 22.3 Initialization and Configuration
  1. 22.3.1 Pin Configuration
  2. 22.3.2 Endpoint Configuration
4. 22.4 USB Global Interrupts
5. 22.5 Software
  1. 22.5.1 USB Examples
6. 22.6 USB Registers
23External Memory Interface (EMIF)
1. 23.1 Introduction
2. 23.2 EMIF Module Architecture
3. 23.3 Example Configuration
  1. 23.3.1 Hardware Interface
  2. 23.3.2 Software Configuration
    1. 23.3.2.1 Configuring the SDRAM Interface
    2. 23.3.2.2 Configuring the Flash Interface
      1. 23.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
4. 23.4 EMIF Registers
24Configurable Logic Block (CLB)
1. 24.1 Introduction
  1. 24.1.1 CLB Related Collateral
2. 24.2 Description
  1. 24.2.1 CLB Clock
3. 24.3 CLB Input/Output Connection
4. 24.4 CLB Tile
5. 24.5 CPU Interface
  1. 24.5.1 Register Description
  2. 24.5.2 Non-Memory Mapped Registers
6. 24.6 DMA Access
7. 24.7 Software
  1. 24.7.1 CLB Examples
8. 24.8 CLB Registers
25Revision History

MCMPF32 MRa, #16FHi

32-Bit Floating-Point Compare for Equal, Less Than or Greater Than

Operands

MRa	CLA floating-point source register (MR0 to MR3)
#16FHi	A 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0.

Opcode

LSW: IIII IIII IIII IIII 
MSW: 0111 1000 1100 00aa

Description

Compare the value in MRa with the floating-point value represented by the immediate operand. Set the ZF and NF flags on (MRa - #16FHi:0).

#16FHi is a 16-bit immediate value that represents the upper 16-bits of an IEEE 32-bit floating-point value. The low 16-bits of the mantissa are assumed to be all 0. This addressing mode is most useful for constants where the lowest 16-bits of the mantissa are 0. Some examples are 2.0 (0x40000000), 4.0 (0x40800000), 0.5 (0x3F000000), and -1.5 (0xBFC00000). The assembler accepts either a hex or float as the immediate value. That is, -1.5 can be represented as #-1.5 or #0xBFC0.

The MCMPF32 instruction is performed as a logical compare operation. This is possible because of the IEEE floating-point format offsets the exponent. Basically the bigger the binary number, the bigger the floating-point value.

Special cases for inputs:

Negative zero is treated as positive zero.
Denormalized value is treated as positive zero.
Not-a-Number (NaN) is treated as infinity.

Flags

This instruction modifies the following flags in the MSTF register:

Flag	TF	ZF	NF	LUF	LVF
Modified	No	Yes	Yes	No	No

The MSTF register flags are modified as follows:

If(MRa == #16FHi:0) {ZF=1, NF=0;}
If(MRa > #16FHi:0) {ZF=0, NF=0;}
If(MRa < #16FHi:0) {ZF=0, NF=1;}

Pipeline

This is a single-cycle instruction

Example 1

; Behavior of ZF and NF flags for different comparisons 
  MMOVIZ      MR1, #-2.0  ; MR1 = -2.0 (0xC0000000) 
  MMOVIZ      MR0, #5.0   ; MR0 = 5.0 (0x40A00000) 
  MCMPF32     MR1, #-2.2  ; ZF = 0, NF = 0 
  MCMPF32     MR0, #6.5   ; ZF = 0, NF = 1 
  MCMPF32     MR0, #5.0   ; ZF = 1, NF = 0

Example 2

; X is an array of 32-bit floating-point values
; and has length elements. Find the maximum value in 
; the array and store the value in Result 
; 
; Note: MCMPF32 and MSWAPF can be replaced with MMAXF32 
; 
_Cla1Task1: 
  MMOVI16 MAR1,#_X        ; Start address 
  MUI16TOF32 MR0, @_len   ; Length of the array 
  MNOP                    ; delay for MAR1 load 
  MNOP                    ; delay for MAR1 load 
  MMOV32 MR1, *MAR1[2]++  ; MR1 = X0 
LOOP 
  MMOV32 MR2, *MAR1[2]++  ; MR2 = next element
  MCMPF32 MR2, MR1        ; Compare MR2 with MR1 
  MSWAPF MR1, MR2, GT     ; MR1 = MAX(MR1, MR2) 
  MADDF32 MR0, MR0, #-1.0 ; Decrememt the counter 
  MCMPF32 MR0 #0.0        ; Set/clear flags for MBCNDD 
  MNOP 
  MNOP 
  MNOP 
  MBCNDD LOOP, NEQ        ; Branch if not equal to zero 
  MMOV32 @_Result, MR1    ; Always executed
  MNOP                    ; Always executed 
  MNOP                    ; Always executed 
  MSTOP                   ; End of task