Once the application requirements are understood,
a specific clock configuration can be determined. The default configuration is for
INTOSC2 to be used as the system clock (PLLSYSCLK) with a divider of 1. The
following procedure must be used to set up the desired application
configuration:
- Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL.
- Set up the system PLL: (see the InitSysPll() function in your devices controlSUITE installation for an example):
- Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN].
- Set the system clock divider to /1 to make sure
of the fastest PLL configuration by clearing SYSCLKDIVSEL[
PLLSYSCLKDIV].
- Set the integral and fractional multipliers by simultaneously writing them both to SYSPLLMULT. This automatically enables the PLL. Be sure that the product of OSCCLK and the multiplier is in the range specified in the data sheet.
- Lock the PLL five times (see your device errata
for details). This number can be increased depending on application
requirements. A higher number of lock attempts helps to make sure of a
successful PLL start.
- Set the system clock divider one setting higher than the final desired value. For example ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1. This limits the current increase when switching to the PLL.
- Set up the watchdog to reset the device. Note
that the SCRS[WDOVERRIDE] bit must not be cleared prior to locking the
PLL.
- Set the SYSDBGCTL[BIT_0] bit. This bit is only reset by a POR reset. If the watchdog has to reset the device due to an issue with switching to the PLL, this bit can be checked in the reset handler to determine the reset was caused by a PLL error.
- Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN].
- Clear the SYSDBGCTL[BIT_0] bit.
- Change the divider to the appropriate value.
- Reconfigure the watchdog as needed for the application.