SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
32-Bit Floating-Point Subtraction
MRa | CLA floating-point destination register (MR0 to R1) |
MRb | CLA floating-point source register (MR0 to R1) |
MRc | CLA floating-point source register (MR0 to R1) |
LSW: 0000 0000 00cc bbaa
MSW: 0111 1100 0100 0000
Subtract the contents of two floating-point registers
MRa = MRb - MRc;
This instruction modifies the following flags in the MSTF register:
Flag | TF | ZF | NF | LUF | LVF |
---|---|---|---|---|---|
Modified | No | No | No | Yes | Yes |
The MSTF register flags are modified as follows:
This is a single-cycle instruction.
; Given A, B, and C are 32-bit floating-point numbers
; Calculate Y2 = A + B - C
;
_Cla1Task5:
MMOV32 MR0, @_A ; Load MR0 with A
MMOV32 MR1, @_B ; Load MR1 with B
MADDF32 MR0, MR1, MR0 ; Add A + B
|| MMOV32 MR1, @_C ; and in parallel load C
MSUBF32 MR0, MR0, MR1 ; Subtract C from (A + B)
MMOV32 @Y, MR0 ; (A+B) - C
MSTOP ; end of task