SPRUHM9H October 2014 – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076
The first step of the receiver configuration procedure is to reset the receiver, and the last step is to enable the receiver (to take the receiver out of reset). Table 20-18 describes the bits used for both of these steps.
Register | Bit | Field | Value | Description |
---|---|---|---|---|
SPCR2 | 7 | FRST | Frame-synchronization logic reset | |
0 | Frame-synchronization logic is reset. The sample rate generator does not generate frame-synchronization signal FSG, even if GRST = 1. | |||
1 | If GRST = 1, frame-synchronization signal FSG is generated after (FPER + 1) number of CLKG clock cycles; all frame counters are loaded with their programmed values. | |||
SPCR2 | 6 | GRST | Sample rate generator reset | |
0 | Sample rate generator is reset. If GRST = 0 due to a DSP reset, CLKG is driven by the CPU clock divided by 2, and FSG is driven low (inactive). If GRST = 0 due to program code, CLKG and FSG are both driven low (inactive). | |||
1 | Sample rate generator is enabled. CLKG is driven according to the configuration programmed in the sample rate generator registers (SRGR[1,2]). If FRST = 1, the generator also generates the frame-synchronization signal FSG as programmed in the sample rate generator registers. | |||
SPCR1 | 0 | RRST | Receiver reset | |
0 | The serial port receiver is disabled and in the reset state. | |||
1 | The serial port receiver is enabled. |