SPRUIF3B May 2017 – March 2019 DRA790 , DRA791 , DRA793 , DRA797
Due to the high level of multiplexing on the SoC (over 16 levels), multiplex control logic is required to use different signals on the same SoC pins with their various functionality. The following information provides description of the logic.
An I2C-based I/O expander controls the onboard MUXs. Table 14 lists the specific bits assigned to each MUX, as well as the specific settings for the various selections.
MUX | Control Bits | Value | MUX Setting |
---|---|---|---|
A | NA | NA | QSPI Memory (default) |
NA | NOR Memory (requires resistor change) | ||
C
(RU4) |
SW8.3 | Off | NOR Memory |
On | EMMC Memory | ||
EXP3.P[15:14] | 00 | EMMC Memory | |
01 | Memory selected by SW8.3 | ||
10 | NOR Memory | ||
11 | Memory selected by SW8.3 (default) | ||
B
(RU9, RU11, RU24) |
EXP2.P[7,0] | 00 | Reserved |
01 | VIN1A to Expansion | ||
10 | VOUT3 to LCD Panel | ||
11 | GPMC NOR/NAND (default) | ||
D
(RU6) |
EXP3.P[6,2] | 00 | Reserved |
01 | Peripheral selected by MUX E (desired default) | ||
10 | VIN2A to Expansion | ||
11 | Open (default) | ||
E
(RU12, RU23) |
EXP2.P[17,14] | 00 | Reserved |
01 | VOUT2 to FPD-Link III Transmitter | ||
10 | VIN2A to LI Camera | ||
11 | EMU (default) | ||
F
(RU27) |
EXP3.P[12,11] | 00 | Reserved |
01 | Peripheral selected by MUX E | ||
10 | VIN2A to Expansion | ||
11 | RGMII1 to Ethernet Port 1 (default) | ||
K
(RJ12) |
EXP2.P16 | 0 | UART3 to COM8Q |
1 | Route to Expansion (SPI2) (default) | ||
L
(RU18) |
EXP2.P3 | 0 | Route to Expansion (I2C3) |
1 | Route to DCAN2 Connector (default) | ||
J
(RU25) |
EXP2.P4 | 0 | Route to Expansion (VIN1B) |
1 | RGMII0 to Ethernet Port 0 (default) | ||
M
(RU8) |
EXP3.P13 | 0 | Route to Expansion (VIN2B) |
1 | Route to Expansion (MMC3/legacy) (default) | ||
G
(RU26) |
SW8.7 | Off | Use Default NOR Address (default) |
On | Use Alternate NOR Address (with EMMC) | ||
H
(RU10) |
EXP3.P1 | 0 | Route to COM8Q (MASP3/7) |
1 | Route to Expansion (McASP3/7) (default) |