VCOP’s vector registers have 8 lanes. Each stores 40 bits. Some arithmetic operations operate on all 40 bits of each lane. Others operate on fewer bits. Data in memory are signed or unsigned 8, 16, or 32 bit integers, which are sign or zero extended to 40 bits when loaded, and truncated or rounded when stored.

C7x has 512-bit vector registers, with variable-width lanes. That is, a vector register can hold 64 lanes of 8-bit data, 32 lanes of 32-bit data, and so on. To achieve efficient translation for the majority of cases, the migration tool will model VCOP’s 40-bit arithmetic using 32-bit lanes. This can cause loss of precision for some kernels that depend on the extra 8 guard bits.