SPRUIM6A October   2018  – November 2020

 

  1. 1Introduction
    1. 1.1 Key Features
  2. 2AM65x IDK Overview
  3. 3Common Processor Board
    1. 3.1 Key Features
    2. 3.2 Functional Block Diagram
    3. 3.3 Overview of Common Processor Board
      1. 3.3.1  Clocking
        1. 3.3.1.1 RTC Clock
        2. 3.3.1.2 Maxwell SoC Clock
        3. 3.3.1.3 Ethernet PHY Clocks
        4. 3.3.1.4 SERDES Clock
      2. 3.3.2  Reset
      3. 3.3.3  Power Requirements
        1. 3.3.3.1 Power Input
        2. 3.3.3.2 Overvoltage and Undervoltage Protection Circuit
        3. 3.3.3.3 Voltage Supervisor
        4. 3.3.3.4 Current Monitoring
        5. 3.3.3.5 Power Supply
        6. 3.3.3.6 Power Sequencing
        7. 3.3.3.7 SoC Power
      4. 3.3.4  Configuration
        1. 3.3.4.1 Boot Modes
        2. 3.3.4.2 JTAG
          1. 3.3.4.2.1 Test Automation
        3. 3.3.4.3 UART Interface
      5. 3.3.5  Memory Interfaces
        1. 3.3.5.1 DDR4 Interface
        2. 3.3.5.2 MMC Interface
          1. 3.3.5.2.1 SDHC Interface
          2. 3.3.5.2.2 eMMC Interface
        3. 3.3.5.3 OSPI Interface
        4. 3.3.5.4 SPI NOR Flash Interface
        5. 3.3.5.5 Board ID EEPROM Interface
        6. 3.3.5.6 Boot EEPROM Interface
      6. 3.3.6  Ethernet Interface
        1. 3.3.6.1 Gigabit Ethernet PHY Default Configuration
        2. 3.3.6.2 Ethernet LEDs
      7. 3.3.7  LCD Display Interface
      8. 3.3.8  USB 2.0 Interface
      9. 3.3.9  CSI-2 Interface
      10. 3.3.10 Application Card Interface
      11. 3.3.11 SERDES Interface
      12. 3.3.12 GPMC/DSS Interface
      13. 3.3.13 I2C Interface
      14. 3.3.14 SPI Interface
      15. 3.3.15 Timer and Interrupt
        1. 3.3.15.1 Timer
        2. 3.3.15.2 Interrupt
      16. 3.3.16 Fan Connector
  4. 4IDK Application Card
    1. 4.1 Key Features
    2. 4.2 Overview of IDK Application Board
      1. 4.2.1 Application Card Connector
      2. 4.2.2 Profibus Interface
      3. 4.2.3 CAN Interface
      4. 4.2.4 Rotary Switch
      5. 4.2.5 Industrial I/O Terminal Connector
      6. 4.2.6 Ethernet Interface
      7. 4.2.7 Board ID Memory
      8. 4.2.8 Power Supply
  5. 5x2 Lane PCIe Personality Card
    1. 5.1 Key Features
    2. 5.2 Overview of PCIex2 Daughter Card
      1. 5.2.1 Personality Card Connectors
      2. 5.2.2 USB 2.0 Interface
      3. 5.2.3 PCIe Interface
      4. 5.2.4 x2 Lane PCIe Personality Card Clocking
      5. 5.2.5 Board ID EEPROM Interface
      6. 5.2.6 x2 Lane PCIe Personality Card Power
  6. 6Known Issues
    1. 6.1 Determining the Revision and Date Code for the EVM
    2. 6.2 Known Issues for the A, E4, and E3 Revision
      1. 6.2.1 Lack of Reset for I2C IO Expander
    3. 6.3 Known Issues for the E4 & E3 Revision
      1. 6.3.1 Changes Unique to the E4 Revision Modified for 2.0 Revision
    4. 6.4 Known Issues for the E3 Revision
      1. 6.4.1 Resonance Observed on the SoC Side of Some Filters Associated with VDDA_1V8
      2. 6.4.2 Additional LDO Power Supply Needed for VDDA_1P8_SERDES0
      3. 6.4.3 Length of the RESET Signal to the PCIE Connectors on the SERDES Daughter Card
      4. 6.4.4 The PORz_OUT and MCU_PORz_OUT Signals Go High During Power Sequencing
      5. 6.4.5 Orientation of the Current Monitoring Shunt Resistors
      6. 6.4.6 SD Card IO Supply Capacitance
      7. 6.4.7 PHY Resistor Strapping Changed to Disable EEE Mode
      8. 6.4.8 The I2C Address for the I2C Boot Memory changed to 0x52
  7. 7Configuring the PRG0 and PRG1 Ethernet Interface to MII
    1. 7.1 Ethernet PHY Initial Conditions and TX Clock Signal Change
      1. 7.1.1 Ethernet PHY0 Clock and Initial Condition for MII
      2. 7.1.2 Ethernet PHY1 Clock and Initial Condition for MII
      3. 7.1.3 Ethernet PHY2 Clock and Initial Condition for MII
      4. 7.1.4 Ethernet PHY3 Clock and Initial Condition for MII
    2. 7.2 Ethernet PHY and TX Data Signals Change
      1. 7.2.1 Ethernet PHY0 TX Data Signals for MII
      2. 7.2.2 Ethernet PHY1 TX Data Signals for MII
      3. 7.2.3 Ethernet PHY2 TX Data Signals for MII
      4. 7.2.4 Ethernet PHY3 TX Data Signals for MII
  8. 8Revision History

4.2.6 Ethernet Interface

Four RGMII/MII ports from the ICSSG domain of the AM65x processor are terminated to the application card connector. These ports in the IDK application board are connected to Gigabit Ethernet PHYs, and the output of the PHYs are terminated with RJ45 connectors (J1 and J3 stacked RJ45 connectors) with integrated magnetic.

All RJ45 ports support 1000 Mbps / 100 Mbps / 10 Mbps using RGMII, and 100 Mbps / 10 Mbps using MII.

From the Ethernet PHY, LED1 and COL/GPIO are connected to dual LEDs of RJ45 to indicate 10/100 Mb or 1000-Mb link. The green LED indicates 10/100-Mb speed, and the orange LED indicates 1000-Mb speed.

LED2 is connected to RJ45 LED (Yellow) to indicate transmit/receive activity.

The IDK application board is delivered with all PHYs configured to operate in RGMII mode. Some industrial protocols require the use of the MII interface instead of RGMII. To change the interface to MII mode, modifications must be made, as shown in Table 4-6.

Table 4-6 Modifications for MII Mode of Operation
PHYMountUnmount
PHY 0R271R269
R272R270
R274R273
R276R275
R278R277
R290R452
R444
R445
R453
PHY 1R317R315
R318R316
R320R319
R322R321
R324R323
R338R454
R446
R447
R455
PHY 2R356R355
R359R357
R361R358
R363R360
R364R362
R378R456
R448
R449
R457
PHY 3R399R397
R400R398
R403R401
R405R402
R406R404
R420R458
R450
R451
R459

Default strapping details of all the PHYs are listed in Table 4-7.

Table 4-7 Ethernet Strap Settings for RGMII and MII Mode
MII Mode Strap SettingRGMII Mode Strap Setting
SignalModePull UpPull DownModePull UpPull Down
PHY0 (J3A) (PHY Address-00000)RX_D01OpenOpen1OpenOpen
RX_D21OpenOpen1OpenOpen
RX_D435.76k2.49k1OpenOpen
RX_D51OpenOpen1OpenOpen
RX_D635.76k2.49k1OpenOpen
RX_D71OpenOpen1OpenOpen
RX_DV/RX_CTRL35.76k2.49k35.76k2.49k
CRS210k2.49k210k2.49k
LED_135.76k2.49k1OpenOpen
LED_01OpenOpen1OpenOpen
PHY1 (J3B) (PHY Address-00011)RX_D042.49KOpen42.49KOpen
RX_D21OpenOpen1OpenOpen
RX_D435.76k2.49k1OpenOpen
RX_D51OpenOpen1OpenOpen
RX_D635.76k2.49k1OpenOpen
RX_D71OpenOpen1OpenOpen
RX_DV/RX_CTRL35.76k2.49k35.76k2.49k
CRS210k2.49k210k2.49k
LED_135.76k2.49k1OpenOpen
LED_01OpenOpen1OpenOpen
PHY2 (J1A) (PHY Address-00000)RX_D01OpenOpen1OpenOpen
RX_D21OpenOpen1OpenOpen
RX_D435.76k2.49k1OpenOpen
RX_D51OpenOpen1OpenOpen
RX_D635.76k2.49k1OpenOpen
RX_D71OpenOpen1OpenOpen
RX_DV/RX_CTRL35.76k2.49k35.76k2.49k
CRS210k2.49k210k2.49k
LED_135.76k2.49k1OpenOpen
LED_01OpenOpen1OpenOpen
PHY3 (J1B) (PHY Address-00011)RX_D042.49KOpen42.49KOpen
RX_D21OpenOpen1OpenOpen
RX_D435.76k2.49k1OpenOpen
RX_D51OpenOpen1OpenOpen
RX_D635.76k2.49k1OpenOpen
RX_D71OpenOpen1OpenOpen
RX_DV/RX_CTRL35.76k2.49k35.76k2.49k
CRS210k2.49k210k2.49k
LED_135.76k2.49k1OpenOpen
LED_01OpenOpen1OpenOpen
GUID-B1059CA4-A1A6-442B-8826-E8A802E8BFD5-low.pngFigure 4-3 PRG0 and PRG1 Ethernet Strapping Diagram in RGMII Mode
GUID-4BDCD031-2F69-4046-9C36-E6A66318E403-low.pngFigure 4-4 PRG0 and PRG1 Ethernet Strapping Diagram in MII Mode
Note:

Resistors marked with the red color box are DNI for those particular modes of operation.

Some of the GPIOs are used to indicate Ethernet activities, as shown in Figure 4-5.

GUID-78EABFD2-2722-4C14-9DFC-3CFD4AE1391A-low.pngFigure 4-5 IDK Board Ethernet LEDs
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