The following steps explain the FIFO features and help with programming the SCI with FIFOs.
- Reset. At reset the SCI powers up in
standard SCI mode and the FIFO function is disabled. The FIFO registers
SCIFFTX, SCIFFRX, and SCIFFCT remain inactive.
- Standard SCI. The standard SCI modes work
normally with TXINT/RXINT interrupts as the interrupt source for the
module.
- FIFO enable. FIFO mode is enabled by
setting the SCIFFEN bit in the SCIFFTX register. SCIRST can reset the FIFO
mode at any stage of the operation.
- Active registers. All the SCI registers
and SCI FIFO registers (SCIFFTX, SCIFFRX, and SCIFFCT) are active.
- Interrupts. FIFO mode has two interrupts;
transmit FIFO (TXINT) and receive FIFO (RXINT). The RXINT is the common
interrupt for SCI FIFO receive, receive error, and receive FIFO overflow
conditions. The TXINT of the standard SCI is disabled and this interrupt
serves as SCI transmit FIFO interrupt.
- Buffers. Transmit and receive buffers are
supplemented with two 16-level FIFOs. The transmit FIFO registers are 8-bits wide and
receive FIFO registers are 10-bits wide. The one-word transmit buffer
(SCITXBUF) of the standard SCI functions as a transition buffer before the
transmit FIFO and shift register. SCITXBUF is loaded into either the FIFO
(when FIFO is enabled) or the TXSHF (when FIFO is disabled). When FIFO is
enabled, SCITXBUF loads into the FIFO only after the last bit of the shift
register is shifted out, so SCITXBUF cannot be treated as an additional
level of buffer. With the FIFO enabled, TXSHF is directly loaded from the
FIFO (not TXBUF) after an optional delay value (SCIFFCT). When FIFO mode is
enabled for SCI, characters written to SCITXBUF are queued in to SCI-TXFIFO
and the characters received in SCI-RXFIFO can be read using SCIRXBUF.
- Delayed transfer. The rate that words in
the FIFO are transferred to the transmit shift register is programmable. The
SCIFFCT register bits (7−0) FFTXDLY7−FFTXDLY0 define the delay between the
word transfer. The delay is defined in the number SCI baud clock cycles. The
8 bit register can define a minimum delay of 0 baud clock cycles and a
maximum of 256-baud clock cycles. With zero delay, the SCI module can
transmit data in continuous mode with the FIFO words shifting out back to
back. With the 256 clock delay the SCI module can transmit data in a maximum
delayed mode with the FIFO words shifting out with a delay of 256 baud
clocks between each words. The programmable delay facilitates communication
with slow SCI/UARTs with little CPU intervention.
- FIFO status bits. Both the transmit and
receive FIFOs have status bits TXFFST or RXFFST (bits 12−8) that define the
number of words available in the FIFOs at any time. The transmit FIFO reset
bit TXFIFO and receive reset bit RXFIFO reset the FIFO pointers to zero when
these bits are cleared to 0. The FIFOs resumes operation from start once
these bits are set to 1.
- Programmable interrupt levels. Both
transmit and receive FIFO can generate CPU interrupts. The interrupt trigger
is generated whenever the transmit FIFO status bits TXFFST (bits 12−8) match
(less than or equal to) the interrupt trigger level bits TXFFIL (bits 4−0).
This provides a programmable interrupt trigger for transmit and receive
sections of the SCI. Default value for these trigger level bits is 0x11111
for receive FIFO and 0x00000 for transmit FIFO, respectively.
Figure 26-10 and Table 26-4 explain the operation/configuration of SCI interrupts in nonFIFO/FFO mode.
Table 26-4 SCI Interrupt Flags
FIFO Options(1) |
SCI Interrupt Source |
Interrupt Flags |
Interrupt Enables |
FIFO Enable SCIFFENA |
Interrupt Line |
SCI without FIFO |
Receive error |
RXERR(2) |
RXERRINTENA |
0 |
RXINT |
Receive break |
BRKDT |
RX/BKINTENA |
0 |
RXINT |
Data receive |
RXRDY |
RX/BKINTENA |
0 |
RXINT |
Transmit empty |
TXRDY |
TXINTENA |
0 |
TXINT |
SCI with FIFO |
Receive error and receive break |
RXERR |
RXERRINTENA |
1 |
RXINT |
FIFO receive |
RXFFIL |
RXFFIENA |
1 |
RXINT |
Transmit empty |
TXFFIL |
TXFFIENA |
1 |
TXINT |
Auto-baud |
Auto-baud detected |
ABD |
Don’t care |
x |
TXINT |
(1) FIFO mode TXSHF is directly loaded after delay value, TXBUF is
not used.
(2) RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag.