The SCI receiver and transmitter can be interrupt controlled. The SCICTL2 register has one flag bit (TXRDY) that indicates active interrupt conditions, and the SCIRXST register has two interrupt flag bits (RXRDY and BRKDT), plus the RX ERROR interrupt flag that is a logical-OR of the FE, OE, BRKDT, and PE conditions. The transmitter and receiver have separate interrupt-enable bits. When not enabled, the interrupts are not asserted; however, the condition flags remain active, reflecting transmission and receipt status.
The SCI has independent peripheral interrupt vectors for the receiver and transmitter. Peripheral interrupt requests can be either high priority or low priority. This is indicated by the priority bits that are output from the peripheral to the PIE controller. When both RX and TX interrupt requests are made at the same priority level, the receiver always has higher priority than the transmitter, reducing the possibility of receiver overrun.
The operation of peripheral interrupts is
described in the Peripheral Interrupts section of the System Control and
Interrupts chapter.
- If the RX/BK INT ENA bit (SCICTL2, bit 1) is set, the receiver peripheral interrupt request is asserted when one of the following events occurs:
- The SCI receives a complete frame and transfers the data in the RXSHF register to the SCIRXBUF register. This action sets the RXRDY flag (SCIRXST, bit 6) and initiates an interrupt.
- A break detect condition occurs (the SCIRXD is low for 9.625 bit periods following a missing stop bit). This action sets the BRKDT flag bit (SCIRXST, bit 5) and initiates an interrupt.
- If the TX INT ENA bit (SCICTL2.0) is set, the transmitter peripheral interrupt request is asserted whenever the data in the SCITXBUF register is transferred to the TXSHF register, indicating that the CPU can write to SCITXBUF; this action sets the TXRDY flag bit (SCICTL2, bit 7) and initiates an interrupt.
Note:
SCI Module Interrupt Reaction Time
- Occasional BRKDT or other errors such as FE/PE being triggered can occur if
there are tight timings occurring in the application.
Interrupts are not triggered until
approximately 7/8 of the stop bit has been detected (approximately 0.875 bit
time). Actual value of this delay before ISR entry is:
((7*BAUD_CLK_PERIOD)/8+3*SYSCLK_PERIOD).
The SCI does not begin reading
additional bits/characters until the RX ISR completes, so complete the ISR
before the next byte's start bit begins. This leaves approximately 1/8 bit time
(approximately 0.125 bit time) to complete the entire ISR, regardless of
interrupt cause.
If the ISR is not completed before
the beginning of the next start bit (before the RX line goes low again), the SCI
module begins reading the start bit late in the wrong location and therefore may
read all bits incorrectly until the next correctly aligned start bit (when ISR
has sufficient time to process before a start bit again).
Recommended methods for avoiding errors (to accommodate for the 0.875 bit time
required for ISR to begin):
- Keep the RX ISR short.
The RX ISR must only be used to move data in the FIFO/buffer into memory
where the data can be processed in another, less time-critical
function.
- Avoid excessive nesting
of other interrupts within the SCI RX ISR. Do not allow the nesting to
delay SCI RX ISR completion past the approximately 0.125 bit time window
allowed.
- If additional time (more
than the approximately 0.125 bit time) is required, delay can be added
in the other device's firmware before transmitting additional data to
the C2000 device's SCI RX pin. Delays can be added to the other device
as follows:
- Sending bytes
with 2 stop bits to the C2000 device provides approximately
1.125 bit time of processing time for C2000 RX ISR to
complete.
- Adding manual
delay in the firmware of the other device transmitting to the
C2000 device after every BYTE transmitted provides (delay +
approximately 0.125 bit time) processing time for the C2000 RX
ISR to complete.
- Adding manual
delay in the firmware of the other device transmitting to the
C2000 device after every C2000 RX INTERRUPT occurs provides
(delay + approximately 0.125 bit time) processing time for the
C2000 RX ISR to complete. This is more difficult to implement
because the other device to predict when the transmitted data
triggers an RX interrupt on the C2000 device is required.
Examples of things that can trigger an RX interrupt are RX-FIFO
level being reached, BRKDT being sent, RXERROR occurring,
etc.
Note: Interrupt generation due to the RXRDY and BRKDT
bits is controlled by the RX/BK INT ENA bit (SCICTL2, bit 1). Interrupt generation
due to the RX ERROR bit is controlled by the RX ERR INT ENA bit (SCICTL1, bit
6).