SPRUJ51 june   2023

 

  1.   1
  2. 1Abstract
  3. 2EVM Revisions and Assembly Variants
    1. 2.1 Inside the Box
    2. 2.2 EMC, EMI and ESD Compliance
  4.   Trademarks
  5. 3System Description
    1. 3.1 Key Features
      1. 3.1.1 Processor
      2. 3.1.2 Power Supply
      3. 3.1.3 Memory
      4. 3.1.4 JTAG Emulator
      5. 3.1.5 Supported Interfaces and Peripherals
      6. 3.1.6 Expansion Connectors Headers to Support Application Specific Add On Boards
    2. 3.2 Functional Block Diagram
    3. 3.3 AM62x-Low Power SK EVM Interface Mapping
    4. 3.4 Power ON OFF Procedures
      1. 3.4.1 Power-On Procedure
      2. 3.4.2 Power-Off Procedure
      3. 3.4.3 Power Test Points
    5. 3.5 Peripheral and Major Component Description
      1. 3.5.1  Clocking
      2. 3.5.2  Reset
      3. 3.5.3  OLDI Display Interface
      4. 3.5.4  CSI Interface
      5. 3.5.5  Audio Codec Interface
      6. 3.5.6  HDMI Display Interface
      7. 3.5.7  JTAG Interface
      8. 3.5.8  Test Automation Header
      9. 3.5.9  UART Interface
      10. 3.5.10 USB Interface
        1. 3.5.10.1 USB 2.0 Type A Interface
        2. 3.5.10.2 USB 2.0 Type C Interface
      11. 3.5.11 Memory Interfaces
        1. 3.5.11.1 LPDDR4 Interface
        2. 3.5.11.2 OSPI Interface
        3. 3.5.11.3 MMC Interfaces
          1. 3.5.11.3.1 MMC0 - eMMC Interface
          2. 3.5.11.3.2 MMC1 - Micro SD Interface
          3. 3.5.11.3.3 MMC2 - M2 Key E Interface
        4. 3.5.11.4 EEPROM
      12. 3.5.12 Ethernet Interface
        1. 3.5.12.1 CPSW Ethernet PHY1 Default Configuration
        2. 3.5.12.2 CPSW Ethernet PHY2 Default Configuration
      13. 3.5.13 GPIO Port Expander
      14. 3.5.14 GPIO Mapping
      15. 3.5.15 Power
        1. 3.5.15.1 Power Requirements
        2. 3.5.15.2 Power Input
        3. 3.5.15.3 Power Supply
        4. 3.5.15.4 Power Sequencing
        5. 3.5.15.5 AM62x 17x17 SoC Power
        6. 3.5.15.6 Current Monitoring
      16. 3.5.16 AM62x-Low Power SK EVM User Setup and Configuration
        1. 3.5.16.1 EVM DIP Switches
        2. 3.5.16.2 Boot Modes
        3. 3.5.16.3 User Test LEDs
      17. 3.5.17 Expansion Headers
        1. 3.5.17.1 User Expansion Connector
        2. 3.5.17.2 MCU Connector
        3. 3.5.17.3 PRU Connector
      18. 3.5.18 Push Buttons
      19. 3.5.19 I2C Address Mapping
  6. 4Known Issues and Modifications
  7. 5Revision History
  8. 6IMPORTANT NOTICE AND DISCLAIMER

3.5.17.2 MCU Connector

The AM62x-Low Power SK EVM has a 14x2 standard 0.1 spaced MCU connector which includes signals connected to the MCU Domain of SoC. 13 Signals include MCU_I2C0, MCU_UART0 (with flow control), MCU_SPI0 and MCU_MCAN0 signals are connected to the MCU Header. Additional control signals provided on the Header include CONN_MCU_RESETz, CONN_MCU_PORz, MCU_RESETSTATz, MCU_SAFETY_ERRORn, 3.3V IO and GND. MCU_UART0 signals from AM62x SoC are connected to both MCU Header and FT4232 Bridge through MUX Mfr Part # SN74CB3Q3257PWR. The MCU Header does not include the Board ID memory interface. Allowed current limit is 100mA on 3.3V rail.

GUID-20221024-SS0I-PCNS-PSMQ-5VL4BXBBLDXX-low.pngFigure 3-28 MCU Connector Interface
Table 3-25 MCU Connector (J10) Pinout
Pin No.SoCBall No.Netname
1-VCC_3V3_SYS
2-DGND
3-DGND
4D8MCU_SPI0_D1
5-CAN_FD_WKUP_HDR_INH
6E8MCU_SPI0_D0
7-DGND
8C8MCU_SPI0_CS1
9-DGND
10D5MCU_GPIO0_15
11D6MCU_GPIO0_16
12B8MCU_UART0_CTS_CONN
13A8MCU_UART0_RXD_CONN
14-DGND
15-DGND
16C5MCU_MCAN0_TX
17D7MCU_UART0_RTS_CONN
18B7MCU_SPI0_CLK
19B6MCU_UART0_TXD_CONN
20-DGND
21A10MCU_I2C0_SDA
22C4MCU_MCAN0_RX
23A12MCU_RESETSTATz
24B9MCU_I2C0_SCL
25-CONN_MCU_RESETz
26-MCU_SAFETY_ERRORz_3V3
27-DGND
28-CONN_MCU_PORz
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