SPRUJ62 December   2022 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

2.4.5 Camera Interfaces [J55] [J57]

The EVM includes dual 40-pin (2x20, 0.5-mm pitch) high speed connectors [J57] [J55] for connecting with cameras and other image capture devices. Each expansion connectors can support up to two CSI2 interfaces. The bandwidth of each CSI2 interface is 10Gbps (4 data lanes each up to 2.5Gbps). The expansion connector(s) also includes power and other IO for communicating with the capture devices. All control signals are configurable for 3.3-V or 1.8-V IO voltage levels. See Section 2.2.2 for configuration details.

Table 2-17 High Speed Camera Expansion Pin Definition [J57][J55]
Pin # Pin Name Description Processor Resource for [J57] / [J55] Dir
1 Power Power, 12 V Output
2 I2C_SCL I2C Bus Clock (I2C5) Bi-Dir
3 Power Power, 12 V Output
4 I2C_SDA I2C Bus Data (I2C5) Bi-Dir
5 CSIa_CLK_P CSI Port 0 / Port 2 Input
6 GPIO0/PWMA IO Expander 0x20 bit P1 / Open Output
7 CSIa_CLK_N CSI Port 0 / Port 2 Input
8 GPIO1/PWMV IO Expander 0x20 bit P2 / bit P4 Bi-Dir
9 CSIa_D0_P CSI Port 0 / Port 2 Input
10 REFCLK 25MHz Reference Clock Output
11 CSIa_D0_N CSI Port 0 / Port 2 Input
12 GND Ground
13 CSIa_D1_P CSI Port 0 / Port 2 Input
14 RESETz GPIO, IO Expander 0x20 bit P0 Output
15 CSIa_D1_N CSI Port 0 / Port 2 Input
16 GND Ground
17 CSIa_D2_P CSI Port 0 / Port 2 Input
18 GPIO2 GPIO0_26 / IO Expander 0x20 bit P5 Bi-Dir
19 CSIa_D2_N CSI Port 0 / Port 2 Input
20 GPIO3 IO Expander 0x20 bit P3 / bit P6 Bi-Dir
21 CSIa_D3_P CSI Port 0 / Port 2 Input
22 GPIO4 GPIO0_28 / IO Expander 0x20 bit P7 Bi-Dir
23 CSIa_D3_N CSI Port 0 / Port 2 Input
24 GND Ground
25 CSIb_CLK_P CSI Port 1 / Open Input
26 CSIb_D3_P CSI Port 1 / Open Input
27 CSIb_CLK_N CSI Port 1 / Open Input
28 CSIb_D3_N CSI Port 1 / Open Input
29 CSIb_D0_P CSI Port 1 / Open Input
30 Power Power, 3.3 V Output
31 CSIb_D0_N CSI Port 1 / Open Input
32 Power Power, 3.3 V Output
33 CSIb_D1_P CSI Port 1 / Open Input
34 Power Power, 3.3 V Output
35 CSIb_D1_N CSI Port 1 / Open Input
36 Power Power, 3.3 V Output
37 CSIb_D2_P CSI Port 1 / Open Input
38 Power Power, IO Level (1.8 V or 3.3 V) Output
39 CSIb_D2_N CSI Port 1 / Open Input
40 Power Power, IO Level (1.8 V or 3.3 V) Output
Note: In the DIR column, output is to the expansion module, input is from the expansion module. Bi-Dir signals can be configured as either input or output.
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