SPRUJ69 December 2022 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The EVM board identity and revision information are stored in an on-board EEPROM. The first 259 bytes of the memory are pre-programmed with EVM identification information. The format of the data is provided in Table 3-6. The remaining bytes are available to user defined storage.
| Field Name | Offset /Size | Value | Comments |
|---|---|---|---|
| MAGIC | 0000 / 4B (Hex) | 0xEE3355AA | Header Identifier |
| M_TYPE | 0004 / 1B (Hex) | 0x01 | Fixed length and variable position board |
| ID header | |||
| M_LENGTH | 0005 / 2B (Hex) | 0x3C | Size of payload |
| B_TYPE | 0007 / 1B (Hex) | 0x10 | Payload type |
| B_LENGTH | 0008 / 2B (Hex) | 0x2E | Offset to next header |
| B_NAME | 000A / 16B (CHAR) | J721S2X-PM1-SOM | Name of the board |
| DESGIN_REV | 001A / 2B (CHAR) | E4 | Revision number of the design |
| PROC_NBR | 001C / 4B (CHAR) | 118 | PROC number |
| VARIANT | 0020 / 2B (CHAR) | 01 | Design variant number |
| PCB_REV | 0022 / 2B (CHAR) | E4 | Revision number of the PCB |
| SCHBOM_REV | 0024 / 2B (CHAR) | E4 | Revision number of the schematic |
| SWR_REV | 0026 / 2B (CHAR) | 01 | first software release number |
| VENDORID | 0028 / 2B (CHAR) | 01 | 0x1: Manufactured by Mistral |
| BUILD_WK | 002A / 2B (CHAR) | 40 | week of the year of production |
| BUILD_YR | 002C / 2B (CHAR) | 22 | year of production |
| BOARDID | 002E / 6B (CHAR) | 0 | |
| SERIAL_NBR | 0034 / 4B (CHAR) | xxxx | incrementing board number |
| DDR_TYPE | 0038 / 1B (Hex) | 0x11 | DDR Header Identifier |
| DDR_LENGTH | 0039 / 2B (Hex) | 0x2 | offset to next header |
| DDR_CONTROL | 003B / 2B (Hex) | 0xC560 |
DDR Control Word Bit 1:0 = ‘00’ First DDR Bit 3:2 = ‘00’ No SPD Bit 5:4 = ‘10’ LPDDR4 Bit 7:6 = ‘01’ 32 bits Bit 9:8 = ‘01’ 32 bits Bit 10 = ‘1’ dual rank Bit 13:11 = ‘000’ Density 64 Gb (bit 0 to 3) Bit 14 = ‘1’ ECC bits present (inline, not separate bits) Bit 15 = ‘1’ Density 64 Gb (bit 4) |
| DDR_TYPE | 003D / 1B (Hex) | 0x11 | DDR Header Identifier |
| DDR_LENGTH | 003E / 2B (Hex) | 0x2 | offset to next header |
| DDR_CONTROL | 0040 / 2B (Hex) | 0xC560 | DDR Control Word |
| DDR_TYPE | 0042 / 1B (Hex) | 0x11 | DDR Header Identifier |
| DDR_LENGTH | 0043 / 2B (Hex) | 0x2 | offset to next header |
| DDR_CONTROL | 0045 / 2B (Hex) | 0xC560 | DDR Control Word |
| DDR_TYPE | 0047 / 1B (Hex) | 0x11 | DDR Header Identifier |
| DDR_LENGTH | 0048 / 2B (Hex) | 0x2 | offset to next header |
| DDR_CONTROL | 004A / 2B (Hex) | 0xC560 | DDR Control Word |
| END_LIST | 0111 / 1B (Hex) | 0xFE | End Marker |