SPRUJ69 December   2022 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Inputs
    2. 2.2 Power Input [J7_CP] with LED for Status [LD2_CP][LD3_CP]
      1. 2.2.1 Power Control [SW2_CP] with LED for Status [LD5_CP] [LD6_CP] [LD7_CP]
      2. 2.2.2 Power Budget Considerations
    3. 2.3 User Inputs
      1. 2.3.1 Board Configuration Settings [SW3_CP] [SW13_CP] [SW3_SOM]
      2. 2.3.2 Boot Configuration Settings [SW9_CP] [SW8_CP]
      3. 2.3.3 Reset Pushbuttons [SW7_CP] [SW6_CP] [SW5_CP] [SW4_CP]
      4. 2.3.4 User Pushbuttons [SW2] [SW11] [SW10] [SW1] [SW12] with User LED Indication [LD9] [LD8]
    4. 2.4 Standard Interfaces
      1. 2.4.1 Uart-Over-USB [J43_CP] [J44_CP] with LED for Status [LD10_CP] [LD11_CP]
      2. 2.4.2 Gigabit Ethernet [J35_CP] with Integrated LEDs for Status
      3. 2.4.3 USB3.1 Gen1 Interface [J5_CP]
      4. 2.4.4 USB2.0 Interface [J6_CP]
      5. 2.4.5 PCIe Card Slot [J8_CP]
      6. 2.4.6 Display Port Interfaces [J36_CP] [J37_CP]
      7. 2.4.7 MicroSD Card Cage [J49_CP]
      8. 2.4.8 Stereo Audio Interface [LINE-IN J38_CP, LINE-OUT J41B_CP, J40B_CP]
    5. 2.5 Expansion Interfaces
      1. 2.5.1 Heatsink [ACC3_SOM] with Fan Header [J15_CP]
      2. 2.5.2 CAN-FD Connectors
      3. 2.5.3 Camera Interfaces [J52_CP]
      4. 2.5.4 Automation and Control Connector [J50_CP]
      5. 2.5.5 ADC [J23_CP]
      6. 2.5.6 CSI-TX [J10_SOM]
      7. 2.5.7 Accessory Power Connector [J42_CP]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
      1. 3.4.1 Power Monitoring
      2. 3.4.2 Shared Interfaces / Signal Muxing
      3. 3.4.3 Power Delivery Network (PDN)
      4. 3.4.4 Identification EEPROM
  5. 4Revision History

3.4.1 Power Monitoring

The EVM includes power monitoring/measurement of 32 discrete power rails. The on-board analog-to-digital converters (INA226) are accessed via I2C. The processor can access using I2C1. The test automation [J50_CP] can access the I2C bus, or it can be access externally via 5-pin header [J12_CP]. Due to the number of rails, the ADCs are split across two I2C buses. Selection of the buses is done via mux setting.

Table 3-5 Power management IC’s
Bus #1 Address Power Rail Nom V Shunt Value Bus #2 Address Power Rail Nom V Shunt Value
0x40 Processor MCU VDD (VDD_MCU_0V85) 0.85 10m-ohm 0x40 Processor IO at 1.8V (VDD_IO_1V8) 1.8 10m-ohm
0x41 Processor MCU VDD (VDD_MCU_RAM_0V85) 0.85 10m-ohm 0x41 Processor IO at 3.3V (VDD_IO_3V3) 3.3 10m-ohm
0x42 (VDA_MCU_1V8) 1.8 10m-ohm 0x42 Processor Dual Voltage IO (VDD_SD_DV) 3.3/1.8 10m-ohm
0x43 Processor MCU IO at 3.3V (VDD_MCUIO_3V3) 3.3 10m-ohm 0x43 LPDDR4 Memory (VDD1) (VDD1_DDR_1V8) 1.8 10m-ohm
0x44 Processor MCU IO at 1.8V (VDD_MCUIO_1V8) 1.8 10m-ohm 0x44 (VDD2Q_DDR_1V1) 1.1 10m-ohm
0x45 (VDD_CORE_0V8) 0.8 5m-ohm 0x45 (VDD_MCUWK_0V8) 0.8 10m-ohm
0x46 (VDD_RAM_0V85) 0.85 10m-ohm 0x46 MCU Peripherals at 1.8V (VSYS_MCUIO_1V8) 1.8 10m-ohm
0x47 (VDD_WK_0V8) 0.8 10m-ohm 0x47 MCU Peripherals at 3.3V (VSYS_MCUIO_3V3) 3.3 10m-ohm
0x48 (VDD_CPU_AVS) 0.8 5m-ohm 0x48 (VSYS_IO_1V8) 1.8 10m-ohm
0x49 (VDD_MCU_GPIORET_3V3) 3.3 10m-ohm 0x49 (VSYS_IO_3V3) 3.3 10m-ohm
0x4A Processor LPDDR IO (VDD_DDR_1V1) 1.1 10m-ohm 0x4A (VCC_12V0) 12 10m-ohm
0x4B (VDD_PHYCORE_0V8) 0.8 10m-ohm 0x4B (VSYS_5V0) 5 10m-ohm
0x4C (VDA_PLL_1V8) 1.8 10m-ohm 0x4C (VSYS_3V3) 3.3 5m-ohm
0x4D (VDD_PHY_1V8) 1.8 10m-ohm 0x4D (VSYS_3V3) 3.3 1m-ohm
0x4E (VDA_USB_3V3) 3.3 10m-ohm 0x4E (VDA_DLL_0V8) 0.8 10m-ohm
0x4F (VDD_GPIORET_3V3) 3.3 10m-ohm 0x4F (EXP_3V3) 3.3 10m-ohm
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