SPRUJ69 December   2022 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Inputs
    2. 2.2 Power Input [J7_CP] with LED for Status [LD2_CP][LD3_CP]
      1. 2.2.1 Power Control [SW2_CP] with LED for Status [LD5_CP] [LD6_CP] [LD7_CP]
      2. 2.2.2 Power Budget Considerations
    3. 2.3 User Inputs
      1. 2.3.1 Board Configuration Settings [SW3_CP] [SW13_CP] [SW3_SOM]
      2. 2.3.2 Boot Configuration Settings [SW9_CP] [SW8_CP]
      3. 2.3.3 Reset Pushbuttons [SW7_CP] [SW6_CP] [SW5_CP] [SW4_CP]
      4. 2.3.4 User Pushbuttons [SW2] [SW11] [SW10] [SW1] [SW12] with User LED Indication [LD9] [LD8]
    4. 2.4 Standard Interfaces
      1. 2.4.1 Uart-Over-USB [J43_CP] [J44_CP] with LED for Status [LD10_CP] [LD11_CP]
      2. 2.4.2 Gigabit Ethernet [J35_CP] with Integrated LEDs for Status
      3. 2.4.3 USB3.1 Gen1 Interface [J5_CP]
      4. 2.4.4 USB2.0 Interface [J6_CP]
      5. 2.4.5 PCIe Card Slot [J8_CP]
      6. 2.4.6 Display Port Interfaces [J36_CP] [J37_CP]
      7. 2.4.7 MicroSD Card Cage [J49_CP]
      8. 2.4.8 Stereo Audio Interface [LINE-IN J38_CP, LINE-OUT J41B_CP, J40B_CP]
    5. 2.5 Expansion Interfaces
      1. 2.5.1 Heatsink [ACC3_SOM] with Fan Header [J15_CP]
      2. 2.5.2 CAN-FD Connectors
      3. 2.5.3 Camera Interfaces [J52_CP]
      4. 2.5.4 Automation and Control Connector [J50_CP]
      5. 2.5.5 ADC [J23_CP]
      6. 2.5.6 CSI-TX [J10_SOM]
      7. 2.5.7 Accessory Power Connector [J42_CP]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
      1. 3.4.1 Power Monitoring
      2. 3.4.2 Shared Interfaces / Signal Muxing
      3. 3.4.3 Power Delivery Network (PDN)
      4. 3.4.4 Identification EEPROM
  5. 4Revision History

2.5.2 CAN-FD Connectors

The EVM supports up to Six [6] CAN Bus interfaces.

Table 2-13 CAN-FD Interface Assignment
Connector Process Resource
J30_CP MCU MCAN0
J31_CP MCU MCAN1
J27_CP MAIN_MCAN3
J28_CP MAIN_MCAN5
J10_SOM MAIN_MCAN16

Each Controller Area Network (CAN) Bus interface is supported on a 3-pin, 2.54-mm pitch header. The interface meets ISO 11898-2 and ISO 11898-5 physical standards and supports CAN and optimized CAN-FD performance up to 8 Mbps. Each includes CAN Bus end-point termination. If the EVM is included in a network with more than two nodes, the termination my need to be adjusted.

Table 2-14 CAN-FD Header Pin Definition
Pin # Pin Name Description Direction
1 CAN-H High-Level CAN Bus Line Bi-Dir
2 GND Ground
3 CAN-L Low-Level CAN Bus Line Bi-Dir
4 WAKE (J30, J27 only) Assert PHY Wake Function Input
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