SPRUJ74 January   2023

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 EMC, EMI, and ESD Compliance
  3. 2QP-ENET Board Identification and Installation
    1. 2.1 QP-ENET Board Component Identification
    2. 2.2 Interfacing QP-ENET Expansion Board with J784S4XG01EVM Board
      1. 2.2.1 Detailed Board Assembly Procedure (J784S4XG01EVM)
  4. 3QP-ENET Expansion Board Hardware Architecture
    1. 3.1 QP-ENET Expansion Board Hardware Top Level Diagram
    2. 3.2 Expansion Connectors
    3. 3.3 Board ID EEPROM
    4. 3.4 Ethernet Interface
      1. 3.4.1 Quad Port SGMII PHY Default Configuration
      2. 3.4.2 SGMII Clocking Scheme
        1. 3.4.2.1 Main Clock
        2. 3.4.2.2 Optional Clock
      3. 3.4.3 Ethernet Port LED Indication
      4. 3.4.4 Reset and Power-down Signals
  5. 4Revision History
  6.   A Appendix
    1.     A.1 Appendix – I (Interface Mapping)
    2.     A.2 Appendix – II (QP-ENET Board GPIO Mapping)

3.4.4 Reset and Power-down Signals

The Reset signal on QP-ENET, QSGMII_RESETz is a reset signal sourced from EVM boards. This signal is used to reset the QSGMII PHY on the board.

QSGMII_RESETz is an AND output of the SOC PORz signal and ENET reset signal. The ENET reset signal is asserted by an I2C GPIO Expander2 (I2C ADD# 0x22, I2C0) on the EVM boards.

The Power-down signal on QP-ENET, ENET_EXP_PWRDN is given by the I2C GPIO Expander2 (I2C ADD# 0x22, I2C0) on the EVM boards; this signal is used to put SGMII PHY on the QP-ENET board to inactive state. By default, this signal has a pull-up on the EVM board, i.e. the PHY is in active state all the time unless low is asserted on this signal.
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