Figure 2-9 shows the reset architecture of the AM261x LaunchPad

Figure 2-9 Reset Architecture

The AM261x LaunchPad has the following resets:

• PORz is the Power On Reset
• WARMRESETn is the warm reset

Figure 2-10 PORZ Reset Signal Tree

The PORz signal is driven by a 2-input AND gate that generates a power on reset for the MAIN domain when:

• The PMIC's(TPS650360) NRSTOUT is driven low .
• The user push button (SW1) is pressed.
• A P-Channel MOSFET gate's signal is logic LOW which causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which is tied directly to ground. The signals that can create the logic LOW input to the PMOS gate are:
  • TA_PORZ output from the Test Automation header
  • BP_PORZ output from either of the BoosterPack sites.

The PORz signal is tied to:

• AM261x SoC PORz input
• Both Ethernet port connector's reset input
• Both OSPI FLASH's reset input
• Boot mode State Driver(U61)'s output enable input
  • There is an RC filter to create a 1ms delay from GND to 3.0V such that the SOP State Driver's output enable input is low longer than the required SOP hold time following a PORz de-assertion.

The WARMRESETn signal creates a warm reset to the MAIN domain when:

• The user push button (SW2) is pressed.

The WARMRESETn signal is tied to:

• AM261x SoC WARMRESETN output
• RESETN_PB signal that is created from push button + PMOS logic

The AM261x LaunchPad also has an external interrupt to the SoC , INT1, that occurs when:

• The user push button (SW3) is pressed.