SPRUJF4 October 2024
The TIEVM-MTR-HVINV implements two redundant overcurrent protection (OCP) circuits. First, an external comparator is capable of reporting an overcurrent fault to the 3-phase inverter. Second, the daughterboard MCU is capable of reporting an overcurrent fault through the use of internal comparators. If either OCP mechanism reports a fault, both the 3-phase inverter and the MCU transition into a fault state. The system remains in a fault state until the state is manually cleared.
Figure 2-12 shows the external OCP circuit. This circuit sums the three current phases, the compares that sum to a reference value. If the summation of the three phase currents ever exceeds the reference value, then the 'IPM_CIN' signal switches and the IPM reports an overcurrent fault to the microcontroller. The exact overcurrent protection current can be calculated by below equations.(1)
First, the reference voltage V- is generated via a voltage divider from the 3.3V power rail.
Next, note that the resistance from any IPM phase to the junction point U10+ is 5.12kΩ. In this scenario, two of the phases (for example, V and W) are at approximately 0A, while the third phase (U) is experiencing a current spike and triggering the OCP circuit. As such, consider RV and Rw in parallel.
The voltage at the junction point U10+ can be referred to as V+. V+ is generated via voltage division relative to the voltage of each phase of the IPM (VU, VV, VW). Note that VV and VW are both assumed to be 0V in this scenario, as IV and IW are both stated to be at or approaching 0A.
VU is also defined as the Voltage across the shunt resistor Rshunt during the overcurrent event.
For the OCP circuit to trigger, V+ must be greater than or equal to the reference voltage V-.
Certain revisions of the board may have higher OCP limits for the external circuit. In these instances, the internal (CMPSS) protection is still fully functional at the intended levels. Refer to Section 6.1 for more information.