Revision(s) Affected

0, A on F2809 silicon

0, A on C2801 and C2802 silicon

0, A, B, C on F2801, F2802, F2806, F2808, F28015, and F28016 silicon

Details

If a GPIO pin is configured for "n" SYSCLKOUT cycle qualification period
(where 1 ≤ n ≤ 510) with "m" qualification samples (m = 3 or 6), it is possible that an input pulse of [n * m – (n – 1)] width may get qualified (instead of n * m). This depends upon the alignment of the asynchronous GPIO input signal with respect to the phase of the internal prescaled clock, and hence, is not deterministic. The probability of this kind of wrong qualification occurring is "1/n".

Worst-case example:

If n = 510, m = 6, a GPIO input width of (n * m) = 3060 SYSCLKOUT cycles is required to pass qualification. However, because of the issue described in this advisory, the minimum GPIO input width which may get qualified is [n * m – (n – 1)] = 3060 – 509 = 2551 SYSCLKOUT cycles.

Workaround(s)

None. Ensure a sufficient margin is in the design for input qualification.