米6体育平台手机版

SPRZ193T January 2003 – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

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1Introduction
2Device and Development Tool Support Nomenclature
3Device Markings
4Usage Notes and Known Design Exceptions to Functional Specifications
1. 4.1 Usage Notes
  1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
5Known Design Exceptions to Functional Specifications
1. Advisory
2. Advisory
3. Advisory
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8. Advisory
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11. Advisory
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27. Advisory
28. Advisory
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30. Advisory
31. Advisory
6Documentation Support
7Trademarks
8Revision History

Advisory

SCI: Incorrect Operation of SCI in Address Bit Mode

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

The SCI does not look for the STOP bit after the ADDR bit. Instead, the SCI starts looking for the start bit beginning on sub-sample 6 of the ADDR bit. Slow rise time from the ADDR bit to the STOP bit can cause a false START bit to occur since the 4th sub-sample for the start bit may be sensed low.

Figure 5-1 Difference Between Expected and Erroneous Operation of START Bit

Workaround(s)

Program the baud rate of the SCI to be slightly slower than the actual. This will cause the 4th sub-sample of the false START bit to be delayed in time, and therefore occur more towards the middle of the STOP bit (away from the signal transition region). The amount of baud-slowing needed depends on the rise time of the signal in the system. Alternatively, the IDLE mode of the SCI module may be used, if applicable.