米6体育平台手机版

SPRZ193T January 2003 – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

1
1Introduction
2Device and Development Tool Support Nomenclature
3Device Markings
4Usage Notes and Known Design Exceptions to Functional Specifications
1. 4.1 Usage Notes
  1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
5Known Design Exceptions to Functional Specifications
1. Advisory
2. Advisory
3. Advisory
4. Advisory
5. Advisory
6. Advisory
7. Advisory
8. Advisory
9. Advisory
10. Advisory
11. Advisory
12. Advisory
13. Advisory
14. Advisory
15. Advisory
16. Advisory
17. Advisory
18. Advisory
19. Advisory
20. Advisory
21. Advisory
22. Advisory
23. Advisory
24. Advisory
25. Advisory
26. Advisory
27. Advisory
28. Advisory
29. Advisory
30. Advisory
31. Advisory
6Documentation Support
7Trademarks
8Revision History

Advisory

Memory: Prefetching Beyond Valid Memory

Revision(s) Affected

0, A, B, C, D, E, F and G

Details

The C28x CPU prefetches instructions beyond those currently active in its pipeline. If the prefetch occurs past the end of valid memory, then the CPU may receive an invalid opcode.

Workaround(s)

The prefetch queue is 8x16 words in depth. Therefore, code should not come within 8 words of the end of valid memory. This restriction applies to all memory regions and all memory types (Flash/ROM, OTP, SARAM, XINTF) on the device. Prefetching across the boundary between two valid memory blocks is fine.

Example 1: M1 ends at address 0x7FF and is not followed by another memory block. Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF should not be used for code.

Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can be stored up to and including address 0x3FF. Code can also cross into M1 up to and including address 0x7F7.