米6体育平台手机版

SPRZ193T January 2003 – December 2023 SM320F2812 , SM320F2812-EP , SMJ320F2812 , TMS320F2810 , TMS320F2810-Q1 , TMS320F2811 , TMS320F2811-Q1 , TMS320F2812 , TMS320F2812-Q1

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1Introduction
2Device and Development Tool Support Nomenclature
3Device Markings
4Usage Notes and Known Design Exceptions to Functional Specifications
1. 4.1 Usage Notes
  1. 4.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear Usage Note
5Known Design Exceptions to Functional Specifications
1. Advisory
2. Advisory
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14. Advisory
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27. Advisory
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30. Advisory
31. Advisory
6Documentation Support
7Trademarks
8Revision History

Advisory

WD: A Low Output on GPIOF14 Can Disable the PLL and Watchdog if the Watchdog Fires a Reset

Revision(s) Affected

0 and A

Details

If, during program execution, the XF_ XPLLDIS/GPIOF14 signal is changed to either of the following:

A general-purpose output and driven low
The XF functionality and driven low

and a watchdog reset occurs, then the low output state of the XF_ XPLLDIS/GPIOF14 pin will be latched into the XPLLDIS signal. The result of this is that the PLL and the reset function of the watchdog will be disabled. The watchdog itself is not disabled.

Workaround(s)

One of the following workarounds can be used:

Do not toggle XF/GPIOF14 in user code. Instead, use another GPIO signal for status.
Set the watchdog to fire an interrupt instead of reset.

This is fixed in the next revision of the silicon.